24.7.5 Bridge Interrupt Flag Status

These flags are cleared by writing a ‘1’ to the corresponding bit.

These flags are set when an access error is detected by the corresponding AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Name:	INTFLAGAHB
Offset:	0x10
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				CRYPTO	BOOTROM	QSPI	PB-D	PB-C
Access				RW	RW	RW	RW	RW
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PB-B	PB-A	PFLASH	CFLASH	SRAM3	SRAM2	SRAM1	SRAM0
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bit 12 – CRYPTO Interrupt Flag for Crypto

This flag is set when an access error is detected by the Crypto AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the crypto interrupt flag.

Bit 11 – BOOTROM Interrupt Flag for Boot ROM

This flag is set when an access error is detected by the Boot ROM Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the Boot ROM interrupt flag.

Bit 10 – QSPI Interrupt Flag for QSPI

This flag is set when an access error is detected by the QSPI AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the QSPI interrupt flag.

Bit 9 – PB-D Interrupt Flag for PB-Bridge-D

This flag is set when an access error is detected by the PB-D AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the PB-D interrupt flag.

Bit 8 – PB-C Interrupt Flag for PB-C (PB-Bridge-C)

This flag is set when an access error is detected by the PB-C Bridge AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the PB-C interrupt flag.

Bit 7 – PB-B Interrupt Flag for PB-B (PB-Bridge-B)

This flag is set when an access error is detected by the PB-B Bridge AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the PB-B interrupt flag.

Bit 6 – PB-A Interrupt Flag for PB-A (PB-Bridge-A)

This flag is set when an access error is detected by the PB-A Bridge AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the PB-A interrupt flag.

Bit 5 – PFLASH Interrupt Flag for PFLASH (Peripheral Flash)

This flag is set when an access error is detected by the PFLASH AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the PFLASH interrupt flag.

Bit 4 – CFLASH Interrupt Flag for CFLASH (CPU Flash)

This flag is set when an access error is detected by the CFLASH AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the CFLASH interrupt flag.

Bit 3 – SRAM3 Interrupt Flag for SRAM3

This flag is set when an access error is detected by the SRAM3 AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the SRAM3 interrupt flag.

Bit 2 – SRAM2 Interrupt Flag for SRAM2

This flag is set when an access error is detected by the SRAM2 AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the SRAM2 interrupt flag.

Bit 1 – SRAM1 Interrupt Flag for SRAM1

This flag is set when an access error is detected by the SRAM1 AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the SRAM1 interrupt flag.

Bit 0 – SRAM0 Interrupt Flag for SRAM0

This flag is set when an access error is detected by the SRAM0 AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit clears the SRAM0 interrupt flag.