24.7.6 Peripheral Interrupt Flag Status - Bridge A

These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to these bits has no effect.

Writing a ‘1’ to these bits clears the corresponding INTFLAGx interrupt flag.

Name:	INTFLAGA
Offset:	0x14
Reset:	0x00000000
Property:	–


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	TCC2	TCC1	TCC0	TC7	TC6	TC5	TC4	TC3
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TC2	TC1	TC0	SERCOM1	SERCOM0	EIC	FREQM	PAC
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bit 15 – TCC2 Interrupt Flag for TCC2

This bit is set when a Peripheral Access Error occurs while accessing the TCC2, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 14 – TCC1 Interrupt Flag for TCC1

This bit is set when a Peripheral Access Error occurs while accessing the TCC1, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 13 – TCC0 Interrupt Flag for TCC0

This bit is set when a Peripheral Access Error occurs while accessing the TCC0, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 12 – TC7 Interrupt Flag for TC7

This bit is set when a Peripheral Access Error occurs while accessing the TC7, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 11 – TC6 Interrupt Flag for TC6

This bit is set when a Peripheral Access Error occurs while accessing the TC6, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 10 – TC5 Interrupt Flag for TC5

This bit is set when a Peripheral Access Error occurs while accessing the TC5, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 9 – TC4 Interrupt Flag for TC4

This bit is set when a Peripheral Access Error occurs while accessing the TC4, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 8 – TC3 Interrupt Flag for TC3

This bit is set when a Peripheral Access Error occurs while accessing the TC3, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 7 – TC2 Interrupt Flag for TC2

This bit is set when a Peripheral Access Error occurs while accessing the TC2, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 6 – TC1 Interrupt Flag for TC1

This bit is set when a Peripheral Access Error occurs while accessing the TC1, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 5 – TC0 Interrupt Flag for TC0

This bit is set when a Peripheral Access Error occurs while accessing the TC0, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 4 – SERCOM1 Interrupt Flag for SERCOM1

This bit is set when a Peripheral Access Error occurs while accessing the SERCOM1, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 3 – SERCOM0 Interrupt Flag for SERCOM0

This bit is set when a Peripheral Access Error occurs while accessing the SERCOM0, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 2 – EIC Interrupt Flag for EIC

This bit is set when a Peripheral Access Error occurs while accessing the EIC, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 1 – FREQM Interrupt Flag for FREQM

This bit is set when a Peripheral Access Error occurs while accessing the FREQM, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.

Bit 0 – PAC Interrupt Flag for PAC

This bit is set when a Peripheral Access Error occurs while accessing the PAC, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the interrupt flag.