22.9.2 Configuration Control Register 1
This register is loaded with trusted data from FBCFG2/DEVCFG1 during the pre-boot period.
Trusted data from Flash means that when there is no BCFG* fail status during Flash, configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication, Reset values (described in the following register description) are retained, and new values from FBCFG2 are not loaded.
Under all conditions, Flash loading is omitted for the ZBTWKSYS bit in CFGCON1 register. Hence, writing this bit in Boot Flash will not have an effect on the configuration register.
Name: | CFGCON1(L) |
Offset: | 0x10 |
Reset: | 0x1f00443b |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
DSRMPM | CLKZBREF | QSPIDDRM | WDTPSS[4:0] | ||||||
Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |
Reset | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
I2CDSEL2 | I2CDSEL1 | I2CDSEL0 | CCL_OE | SCOM_HSEN[1:0] | QSPI_HSEN | ||||
Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
QSCHE_EN | SMCLR | SLRCTRL2 | SLRCTRL1 | SLRCTRL0 | CMP1_OE | CMP0_OE | |||
Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | ||
Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ZBTWKSYS | ECC_SEL_MEM | TRCEN | |||||||
Access | R/W/L | R/W/L | R/W/L | ||||||
Reset | 0 | 0 | 1 |
Bit 31 – DSRMPM Deep Sleep Retention Memory Power Mode
00
’.Value | Description |
---|---|
1 | Only Retention Power mode (reset value) |
0 | NAP + Retention Power mode |
Bit 30 – CLKZBREF External Reference Clock
The external reference clock output from the Zigbee wireless subsystem on the REFO1 pin, which is configurable through PPS.
00
’.Value | Description |
---|---|
1 | Clock from Zigbee wireless subsystem on PPS.REFO1 is enabled |
0 | No clock from Zigbee wireless subsystem on PPS.REFO1 |
Bit 29 – QSPIDDRM QSPI Double Data Rate (DDR) Mode Clock Enable
- When using the QSPI DDR mode, the System Clock (SYS_CLK) must be <= 32 MHz.
- This bit is only writable when CFGLOCK[1:0] is ‘
00
’.
Value | Description |
---|---|
1 | QSPI DDR mode clock is enabled |
0 | QSPI DDR mode clock is disabled |
Bits 28:24 – WDTPSS[4:0] Watchdog Timer Post-scale Select Sleep bits
00
’.Value | Description |
---|---|
10100 | 1:1048576 |
10011 | 1:524288 |
10010 | 1:262144 |
10001 | 1:131072 |
10000 | 1:65536 |
01111 | 1:32768 |
01110 | 1:16384 |
01101 | 1:8192 |
01100 | 1:4096 |
01011 | 1:2048 |
01010 | 1:1024 |
01001 | 1:512 |
01000 | 1:256 |
00111 | 1:128 |
00110 | 1:64 |
00101 | 1:32 |
00100 | 1:16 |
00011 | 1:8 |
00010 | 1:4 |
00001 | 1:2 |
00000 | 1:1 |
Bit 23 – I2CDSEL2 I2C Delay Select for SERCOM2
00
’.Value | Description |
---|---|
1 | I2C delay is enabled. |
0 | I2C delay is disabled. |
Bit 22 – I2CDSEL1 I2C Delay Select for SERCOM1
00
’.Value | Description |
---|---|
1 | I2C delay is enabled |
0 | I2C delay is disabled |
Bit 21 – I2CDSEL0 I2C Delay Select for SERCOM0
00
’.Value | Description |
---|---|
1 | I2C delay is enabled |
0 | I2C delay is disabled |
Bit 20 – CCL_OE CCL Pads (via PPS) Output Enable
00
’.Value | Description |
---|---|
1 | CCL pads (via PPS) output is enabled |
0 | CCL pads (via PPS) output is disabled |
Bits 18:17 – SCOM_HSEN[1:0] SERCOM (Direct) Enable, 17 = SERCOM0 and 18 = SERCOM1
- These bits are only writable when CFGLOCK[1:0] is ‘
00
’. - For the 32-pin variant PIC32CX5109BZ31032 device, QSPI works only with the PPS configuration. It does not work in Direct mode.
Value | Description |
---|---|
1 | Direct mode (High-Speed) is enabled |
0 | Via PPS is enabled |
Bit 16 – QSPI_HSEN QSPI (Direct) Enable
- This bit is only writable when CFGLOCK[1:0] is ‘
00
’. - For the 32-pin variant PIC32CX5109BZ31032 device, QSPI works only with the PPS configuration. It does not work in Direct mode.
Value | Description |
---|---|
1 | Direct Mode (High-Speed) is enabled |
0 | Via PPS is enabled |
Bit 15 – QSCHE_EN QSPI Address Space Cache Attribute
00
’.Value | Description |
---|---|
1 | Cache attribute is enabled |
0 | Caching is disabled |
Bit 14 – SMCLR Selects CRU handling of NMCLR Control
00
’.Value | Description |
---|---|
1 | Does not reset all device NMCLR Reset states |
0 | NMCLR external Reset causes a faux POR |
Bit 13 – SLRCTRL2 I2C Slew Rate Control for SERCOM2
00
’.Value | Description |
---|---|
1 | Slew rate control is configured via SERCOM configuration |
0 | Slew rate control is configured via GPIO configuration |
Bit 12 – SLRCTRL1 I2C Slew Rate Control for SERCOM1
00
’.Value | Description |
---|---|
1 | Slew rate control is configured via SERCOM configuration |
0 | Slew rate control is configured via GPIO configuration |
Bit 11 – SLRCTRL0 I2C Slew Rate Control for SERCOM0
00
’.Value | Description |
---|---|
1 | Slew rate control is configured via SERCOM configuration |
0 | Slew rate control is configured via GPIO configuration |
Bit 9 – CMP1_OE Analog Comparator-1 Output Enable
- This bit is only writable when CFGLOCK[1:0] is ‘
00
’. - Not available in the 32-pin variant PIC32CX5109BZ31032 device
Value | Description |
---|---|
1 | AC_CMP1 output is enabled |
0 | AC_CMP1 output is disabled |
Bit 8 – CMP0_OE Analog Comparator-0 Output Enable
- This bit is only writable when CFGLOCK[1:0] is ‘
00
’. - Not available in the 32-pin variant PIC32CX5109BZ31032 device
Value | Description |
---|---|
1 | AC_CMP0 output is enabled |
0 | AC_CMP0 output is disabled |
Bit 7 – ZBTWKSYS ZBT Subsystem External Wake-up source
- Write-only bit, with read-as zero; when ‘
1
’ is written, creates one pulse on the ZBT subsystem.external_NMI0 pin. This enables external system wake-up to ZBT subsystem. This allows CPU and ZBT subsystem wake-up/sleep to be independent of each other. - Flash fuse loading is excluded for this bit.
Bit 6 – ECC_SEL_MEM ECC Row Selection
This bit comes into effect only for 96K memory variant and if CFGCON0.FRECCDIS = 0
. For other cases, this bit setting has no effect.
00
.Value | Description |
---|---|
1 | RowC ECC is applied for Row B |
0 | RowC ECC is applied for Row A |
Bit 5 – TRCEN Trace Enable
00
’.Value | Description |
---|---|
1 | Trace features in the CPU are enabled |
0 | Trace features in the CPU are disabled |