22.9.2 Configuration Control Register 1

This register is loaded with trusted data from FBCFG2/DEVCFG1 during the pre-boot period.

Trusted data from Flash means that when there is no BCFG* fail status during Flash, configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication, Reset values (described in the following register description) are retained, and new values from FBCFG2 are not loaded.

Under all conditions, Flash loading is omitted for the ZBTWKSYS bit in CFGCON1 register. Hence, writing this bit in Boot Flash will not have an effect on the configuration register.

Name: CFGCON1(L)
Offset: 0x10
Reset: 0x1f00443b
Property: -

Bit 3130292827262524 
 DSRMPMCLKZBREFQSPIDDRMWDTPSS[4:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 00011111 
Bit 2322212019181716 
 I2CDSEL2I2CDSEL1I2CDSEL0CCL_OE SCOM_HSEN[1:0]QSPI_HSEN 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 0000000 
Bit 15141312111098 
 QSCHE_ENSMCLRSLRCTRL2SLRCTRL1SLRCTRL0 CMP1_OECMP0_OE 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 0100000 
Bit 76543210 
 ZBTWKSYSECC_SEL_MEMTRCEN      
Access R/W/LR/W/LR/W/L 
Reset 001 

Bit 31 – DSRMPM Deep Sleep Retention Memory Power Mode

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1 Only Retention Power mode (reset value)
0 NAP + Retention Power mode

Bit 30 – CLKZBREF External Reference Clock

The external reference clock output from the Zigbee wireless subsystem on the REFO1 pin, which is configurable through PPS.

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Clock from Zigbee wireless subsystem on PPS.REFO1 is enabled
0No clock from Zigbee wireless subsystem on PPS.REFO1

Bit 29 – QSPIDDRM QSPI Double Data Rate (DDR) Mode Clock Enable

Note:
  • When using the QSPI DDR mode, the System Clock (SYS_CLK) must be <= 32 MHz.
  • This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1QSPI DDR mode clock is enabled
0QSPI DDR mode clock is disabled

Bits 28:24 – WDTPSS[4:0] Watchdog Timer Post-scale Select Sleep bits

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
101001:1048576
100111:524288
100101:262144
100011:131072
100001:65536
011111:32768
011101:16384
011011:8192
011001:4096
010111:2048
010101:1024
010011:512
010001:256
001111:128
001101:64
001011:32
001001:16
000111:8
000101:4
000011:2
000001:1

Bit 23 – I2CDSEL2 I2C Delay Select for SERCOM2

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1I2C delay is enabled.
0I2C delay is disabled.

Bit 22 – I2CDSEL1 I2C Delay Select for SERCOM1

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1I2C delay is enabled
0I2C delay is disabled

Bit 21 – I2CDSEL0 I2C Delay Select for SERCOM0

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1I2C delay is enabled
0I2C delay is disabled

Bit 20 – CCL_OE CCL Pads (via PPS) Output Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1CCL pads (via PPS) output is enabled
0CCL pads (via PPS) output is disabled

Bits 18:17 – SCOM_HSEN[1:0] SERCOM (Direct) Enable, 17 = SERCOM0 and 18 = SERCOM1

Note:
  • These bits are only writable when CFGLOCK[1:0] is ‘00’.
  • For the 32-pin variant PIC32CX5109BZ31032 device, QSPI works only with the PPS configuration. It does not work in Direct mode.
ValueDescription
1Direct mode (High-Speed) is enabled
0Via PPS is enabled

Bit 16 – QSPI_HSEN QSPI (Direct) Enable

Note:
  • This bit is only writable when CFGLOCK[1:0] is ‘00’.
  • For the 32-pin variant PIC32CX5109BZ31032 device, QSPI works only with the PPS configuration. It does not work in Direct mode.
ValueDescription
1Direct Mode (High-Speed) is enabled
0Via PPS is enabled

Bit 15 – QSCHE_EN QSPI Address Space Cache Attribute

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Cache attribute is enabled
0Caching is disabled

Bit 14 – SMCLR Selects CRU handling of NMCLR Control

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Does not reset all device NMCLR Reset states
0NMCLR external Reset causes a faux POR

Bit 13 – SLRCTRL2 I2C Slew Rate Control for SERCOM2

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Slew rate control is configured via SERCOM configuration
0Slew rate control is configured via GPIO configuration

Bit 12 – SLRCTRL1 I2C Slew Rate Control for SERCOM1

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Slew rate control is configured via SERCOM configuration
0Slew rate control is configured via GPIO configuration

Bit 11 – SLRCTRL0 I2C Slew Rate Control for SERCOM0

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Slew rate control is configured via SERCOM configuration
0Slew rate control is configured via GPIO configuration

Bit 9 – CMP1_OE Analog Comparator-1 Output Enable

Note:
  • This bit is only writable when CFGLOCK[1:0] is ‘00’.
  • Not available in the 32-pin variant PIC32CX5109BZ31032 device
ValueDescription
1AC_CMP1 output is enabled
0AC_CMP1 output is disabled

Bit 8 – CMP0_OE Analog Comparator-0 Output Enable

Note:
  • This bit is only writable when CFGLOCK[1:0] is ‘00’.
  • Not available in the 32-pin variant PIC32CX5109BZ31032 device
ValueDescription
1AC_CMP0 output is enabled
0AC_CMP0 output is disabled

Bit 7 – ZBTWKSYS ZBT Subsystem External Wake-up source

Note:
  • Write-only bit, with read-as zero; when ‘1’ is written, creates one pulse on the ZBT subsystem.external_NMI0 pin. This enables external system wake-up to ZBT subsystem. This allows CPU and ZBT subsystem wake-up/sleep to be independent of each other.
  • Flash fuse loading is excluded for this bit.

Bit 6 – ECC_SEL_MEM ECC Row Selection

This bit comes into effect only for 96K memory variant and if CFGCON0.FRECCDIS = 0. For other cases, this bit setting has no effect.

Note: This bit is only writable when CFGLOCK[1:0] = 00.
ValueDescription
1RowC ECC is applied for Row B
0RowC ECC is applied for Row A

Bit 5 – TRCEN Trace Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Trace features in the CPU are enabled
0Trace features in the CPU are disabled