22.9.5 Permission Group Configuration

All bits in this register are writable only when CFGCON0.PGLOCK = 0.

There is no Flash location for this register because the purpose of this register to provide software based protection mechanism to device memory mapped region.

Name: CFGPGQOS
Offset: 0x50
Reset: 0xe044004c
Property: -

Bit 3130292827262524 
 WISIBQOS[1:0]FCQOS[1:0]  DSUPG[1:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 111000 
Bit 2322212019181716 
 CRYPTOQOS[1:0]CRYPTOPG[1:0]     
Access R/W/LR/W/LR/W/LR/W/L 
Reset 0100 
Bit 15141312111098 
       DMAPG[1:0] 
Access R/W/LR/W/L 
Reset 00 
Bit 76543210 
     CPUQOS[1:0]CPUPG[1:0] 
Access R/W/LR/W/LR/W/LR/W/L 
Reset 1100 

Bits 31:30 – WISIBQOS[1:0] Wireless SIB QOS Control Bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.
ValueDescription
00Disable; Background
01Low; Sensitive bandwidth
10Medium; Sensitive latency
11High; Critical latency

Bits 29:28 – FCQOS[1:0] FC Controller QOS Control Bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.
ValueDescription
00Disable; Background
01Low; Sensitive bandwidth
10Medium; Sensitive latency
11High; Critical latency

Bits 25:24 – DSUPG[1:0] DSU Permission Group

The DSU bus host has access to Access Controlled memory regions in the Bus Structure’s Permission Groups SFRs.
  • DSUPG[1:0] == 2’b11 : Initiator is assigned to Permission Group 3
  • DSUPG[1:0] == 2’b10 : Initiator is assigned to Permission Group 2
  • DSUPG[1:0] == 2’b01 : Initiator is assigned to Permission Group 1
  • DSUPG[1:0] == 2’b00 : Initiator is assigned to Permission Group 0
Note: This field is only writable when CFGCON0.PGLOCK = 0.

Bits 23:22 – CRYPTOQOS[1:0] Crypto QOS Control Bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.
ValueDescription
00Disable; Background
01Low; Sensitive bandwidth
10Medium; Sensitive latency
11High; Critical latency

Bits 21:20 – CRYPTOPG[1:0] Crypto Permission Group

The Crypto bus host has access to Access Controlled memory regions in the Bus Structure’s Permission Groups SFRs.
  • CRYPTOPG[1:0] == 2’b11 : Initiator is assigned to Permission Group 3
  • CRYPTOPG[1:0] == 2’b10 : Initiator is assigned to Permission Group 2
  • CRYPTOPG[1:0] == 2’b01 : Initiator is assigned to Permission Group 1
  • CRYPTOPG[1:0] == 2’b00 : Initiator is assigned to Permission Group 0
Note: This field is only writable when CFGCON0.PGLOCK = 0.

Bits 9:8 – DMAPG[1:0] DMA (Rd/Wr) Permission Group

The DMA bus host has access to Access Controlled memory regions in the Bus Structure’s Permission Groups SFRs.
  • DMAPG[1:0] == 2’b11 : Initiator is assigned to Permission Group 3
  • DMAPG[1:0] == 2’b10 : Initiator is assigned to Permission Group 2
  • DMAPG[1:0] == 2’b01 : Initiator is assigned to Permission Group 1
  • DMAPG[1:0] == 2’b00 : Initiator is assigned to Permission Group 0
Note: This field is only writable when CFGCON0.PGLOCK = 0.

Bits 3:2 – CPUQOS[1:0] CPU I/D and System Bus QOS Control Bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.
ValueDescription
00Disable; Background
01Low; Sensitive bandwidth
10Medium; Sensitive latency
11High; Critical latency

Bits 1:0 – CPUPG[1:0] CPU (Code) Permission Group

The CPU Bus host has access to Access Controlled memory regions in the Bus Structure’s Permission Groups SFRs.
  • CPUPG[1:0] == 2’b11 : Initiator is assigned to Permission Group 3
  • CPUPG[1:0] == 2’b10 : Initiator is assigned to Permission Group 2
  • CPUPG[1:0] == 2’b01 : Initiator is assigned to Permission Group 1
  • CPUPG[1:0] == 2’b00 : Initiator is assigned to Permission Group 0
Note:
  • CPUPG[1:0] automatically reverts to 2’b00 when the CPU acknowledges entering into an NMI exception
  • This field is only writable when CFGCON0.PGLOCK = 0

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