2.4 Unused IP Pin Tie-offs
(Ask a Question)The final section of the device configuration report is the unused IP pin tie-offs. When an IP block is unused in a design, all fabric driven IP block inputs are connected (tied-off) to either a logic '1' or a logic '0'. This tie-off is through an SEU immune FPGA fabric flash bit. The inputs are tied-off to logic levels that places the IP block into a low-power reset state disabling the operation of the block. This section reports all unused IP blocks with the tie-off connection of each FPGA fabric input to the block.