The Configure Register Lock Bits option available in the Libero SoC Design tool is used
to write-protect/lock user selected IP registers. Register lock bits are set in a text
(*.txt) file, which the user then imports into the Libero SoC
project. Use the following procedure in Libero SoC design tool to import the lock bit
file into a design:
From the Design Flow window, double-click
Configure Register Lock Bits to open the
configurator.
Navigate to the text file (*.txt) that contains the register
lock bits settings (see the following figure).
Subsequent FPGA bitstreams generated will have IP register lock bits set according to the
file. Figure 2-4. Register Lock Bit
Settings
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
