2.3 Recommendations for Lock Bits

Transceiver Related IP Blocks
This applies to all transceiver building blocks that are named "Qx_*" and the PCIe building blocks that are named "PCIEx_*". If the Lock Value field is equal to 1, then the register has lock capability. Only registers with the “Register Modified field = No” must be considered for locking. These registers are not modified from their default value so there is no potential to lock out the power-up/DEVRSTn UIC configuration sequence that may dynamically configure the register. Due to interdependencies of these IP blocks, if any transceiver capability is added to the user design, then apply this recommendation to all transceiver-related blocks.
Non-transceiver Related IP Blocks
If the Lock Value field is equal to 1, then the register has lock capability. If the IP block is not used in the design, (the instance name = N/A) then it is safe to lock the IP block. If the IP block is used in the design, then it is safe to lock the IP block when there is no plan/capability to dynamically change the configuration of the IP during design operation.
Block-level Locked IP Blocks
Some IP blocks have a single lock bit for all registers in the block. These IP blocks are listed in the subsection of the report titled "Block-Level Control for locking peripheral blocks".
Figure 2-3. Block-level Control For Locking Peripheral Blocks

If the IP block is not used in the design, (the instance name = N/A) then it is safe to lock the IP block. If the IP block is used in the design, then it is safe to lock the IP block when there is no plan to dynamically change the configuration of the IP during design operation. For example, if the user plans to dynamically change a CCC PLL frequency while the design is operational, then this IP block cannot be locked.