2.1 Register Locks

The PolarFire® family of devices supports register write-protection activated through "lock" bits for the configuration registers of various IP blocks in the device. This write-protection feature enables immunity against SEUs and unintentional writes to configuration registers. Many IP blocks have flip-flop based registers which are initialized by user-configurable flash bits at power-up. After initialization, the registers content can be protected by enabling the write-protection, lock bit feature associated with the register.

The following figure shows a schematic representation of register bit protected by a lock.

If a write-protection flash bit (DYN_REG[x]) is set, then the associated flip-flop is held in continuous reset or preset depending upon its initialization flash bit value (MSS_P[x]). Therefore, even if there is an SEU hit on the flip-flop, the flip-flop immediately goes back to the initialized flash bit value.

Some register content can be read back at run-time, using the DRI interface or an APB interface, to ensure that registers are initialized properly, and have not changed over time.

The register lock capability is provided at the register-level for many of the registers in the transceiver building blocks, user crypto block, TVS, and voltage detector block. Other IP blocks including CCCs and lane controllers have block-level register locking capability.