35.8.6.10 Address

Table 35-59. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: ADDR
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
      ADDRMASK[9:7] 
Access R/WR/WR/W 
Reset 000 
Bit 2322212019181716 
 ADDRMASK[6:0]  
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
 TENBITEN    ADDR[9:7] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 ADDR[6:0]GENCEN 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 26:17 – ADDRMASK[9:0] Address Mask

These bits act as a second address match register, an address mask register, or the lower limit of an address range, depending on the CTRLB.AMODE setting.

Bit 15 – TENBITEN Ten Bit Addressing Enable

ValueDescription
010-bit address recognition disabled.
110-bit address recognition enabled.

Bits 10:1 – ADDR[9:0] Address

These bits contain the I2C client address used by the client address match logic to determine if a host has addressed the client.

When using 7-bit addressing, the client address is represented by ADDR[6:0].

When using 10-bit addressing (ADDR.TENBITEN=1), the client address is represented by ADDR[9:0]

When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate whether it is a read or a write transaction.

Bit 0 – GENCEN General Call Address Enable

A general call address is an address consisting of all-zeroes, including the direction bit (host write).

ValueDescription
0General call address recognition disabled.
1General call address recognition enabled.