35.8.6.4 Interrupt Enable Clear
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENCLR |
| Offset: | 0x14 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | RXFF | TXFE | DRDY | AMATCH | PREC | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error Interrupt Disable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Bit 4 – RXFF RX FIFO Full Interrupt Disable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the RX FIFO Full bit, which disables the RX FIFO Full interrupt.
Bit 3 – TXFE TX FIFO Empty Interrupt Disable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the TX FIFO Empty bit, which disables the TX FIFO Empty interrupt.
Bit 2 – DRDY Data Ready Interrupt Disable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt.
Bit 1 – AMATCH Address Match Interrupt Disable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt.
Bit 0 – PREC Stop Received Interrupt Disable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt.