35.8.6.2 Control B

Table 35-50. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 FIFOCLR[1:0]   ACKACTCMD[1:0] 
Access R/WR/WR/WWW 
Reset 00000 
Bit 15141312111098 
 AMODE[1:0]   AACKENGCMDSMEN 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
          
Access  
Reset  

Bits 23:22 – FIFOCLR[1:0] FIFO Clear

When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.SYSOP = 0.

These bits are not enable-protected.

FIFOCLR[1:0]NameDescription
0x0NONENo action
0x1TXFIFOClear TX FIFO
0x2RXFIFOClear RX FIFO
0x3BOTHClear both TX/RX FIFO

Bit 18 – ACKACT Acknowledge Action

This bit defines the client's acknowledge behavior after an address or data byte is received from the host. The acknowledge action is executed when a command is written to the CMD bits. If smart mode is enabled (CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read.

ACKACT shall not be updated more than once between each peripheral interrupts request.

This bit is not enable-protected. This bit is not write-synchronized.

Note:

CTRLB.ACKACT shall not be updated more than once between each peripheral interrupt request.

ValueDescription
0Send ACK
1Send NACK

Bits 17:16 – CMD[1:0] Command

This bit field triggers the client operation as shown below. The CMD bits are strobe bits, and always read as zero. The operation is dependent on the client interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR.

All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given.

This bit is not enable-protected. This bit is not write-synchronized.

Table 35-51. Command Description
CMD[1:0]STATUS.DIR ValueAction
0x0X(No action)
0x1X(Reserved)
0x2Used to complete a transaction in response to a data interrupt (DRDY)
0 (Host write)Execute acknowledge action succeeded by waiting for any start (S/Sr) condition
1 (Host read)Wait for any start (S/Sr) condition
0x3Used in response to an address interrupt (AMATCH)
0 (Host write)Execute acknowledge action succeeded by reception of next byte
1 (Host read)Execute acknowledge action succeeded by client data interrupt
Used in response to a data interrupt (DRDY)
0 (Host write)Execute acknowledge action succeeded by reception of next byte
1 (Host read)Execute a byte read operation followed by ACK/NACK reception

Bits 15:14 – AMODE[1:0] Address Mode

These bits set the addressing mode.

These bits are not write-synchronized.

ValueNameDescription
0x0MASKThe client responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK.

See SERCOM – Serial Communication Interface for additional information.

0x12_ADDRSThe client responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK.
0x2RANGEThe client responds to the range of addresses: ADDR.ADDRMASK < address < ADDR.ADDR
0x3-Reserved.

Bit 10 – AACKEN Automatic Acknowledge Enable

This bit enables the address to be automatically acknowledged if there is an address match.

This bit is not write-synchronized.

ValueDescription
0Automatic acknowledge is disabled.
1Automatic acknowledge is enabled.

Bit 9 – GCMD PMBus Group Command

This bit enables PMBus group command support. When enabled, the Stop Received interrupt flag (INTFLAG.PREC) will be set when a STOP condition is detected if the client has been addressed since the last STOP condition on the bus.

This bit is not write-synchronized.

ValueDescription
0Group command is disabled.
1Group command is enabled.

Bit 8 – SMEN Smart Mode Enable

When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read.

This bit is not write-synchronized.

ValueDescription
0Smart mode is disabled.
1Smart mode is enabled.