35.8.6.13 FIFO CPU Pointers

Table 35-62. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: FIFOPTR
Offset: 0x36
Reset: 0x0000
Property: -

This register provides a copy of internal CPU TX and RX FIFO pointers.

Bit 15141312111098 
     CPURDPTR[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
     CPUWRPTR[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 11:8 – CPURDPTR[3:0] RX FIFO Pointer

These bits return the CPURDPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. Reading DATA register, will return RXFIFO[CPURDPTR] location value.

Bits 3:0 – CPUWRPTR[3:0] TX FIFO Pointer

These bits return the CPUWRPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. When writing to DATA register, the DATA will be written to TXFIFO[CPUWRPTR] location.