26.7.8 Voltage Regulator System (VREG) Control

Note: During normal operation, all voltage regulators that are in use must be left in the On state to allow for the proper transition between different low-power/standby states.

Table 26-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	VREGCTRL
Offset:	0x001C
Reset:	0x00000004
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
						AVREGSTGBY[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	23	22	21	20	19	18	17	16
						AVREGEN[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	15	14	13	12	11	10	9	8
						CPEN[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	7	6	5	4	3	2	1	0
			BKUP_VLD	SRAM_VLD
Access			R/W/HC	R/W/HC
Reset			0	0

Bits 26:24 – AVREGSTGBY[2:0] Additional Voltage Regulator Configuration

Value	Description
0x0	USB0, USB1 and PLL regulators are off in sleep, standby, hibernate or backup mode
0x1	USB0 Regulator is ON in Standby mode if corresponding AVREGEN bit is set. It is OFF in Hibernate or Backup mode.
0x2	USB1 Regulator is ON in Standby mode if corresponding AVREGEN bit is set. It is OFF in Hibernate or Backup mode.
0x3	USB0 & USB1 Regulators are ON in Standby mode if corresponding AVREGEN bit(s) are set. They are OFF in Hibernate or Backup mode.
0x4	PLL Regulators is ON in Standby mode if corresponding AVREGEN bit is set. It is OFF in Hibernate or Backup mode.
0x5	USB0 & PLL regulators are ON in Standby mode if corresponding AVREGEN bit(s) are set. They are OFF in Hibernate or Backup mode.
0x6	USB1 & PLL regulators are ON in Standby mode if corresponding AVREGEN bit(s) are set. They are OFF in Hibernate or Backup mode.
0x7	USB0, USB1 and PLL regulators are ON in Standby mode if corresponding AVREGEN bit(s) are set. They are OFF in Hibernate or Backup mode.

Bits 18:16 – AVREGEN[2:0] Additional Voltage Regulator Enabled

Note: The USB0 and USB1 regulators should be enabled one at a time, when needed, with at least 1us of delay between the enabling event for each.

Value	Description
0x0	USB0, USB1 and PLL regulators disabled (Default)
0x1	USB0 Regulator Enabled
0x2	USB1 Regulator Enabled
0x3	USB0 & USB1 Regulators Enabled
0x4	PLL Regulators enabled
0x5	USB0 & PLL regulators enabled
0x6	USB1 & PLL regulators enabled
0x7	USB0, USB1 and PLL regulators enabled

Bits 10:8 – CPEN[2:0] Analog Peripheral Charge Pump Enabled


Value	Description	Requirements
0x0	All charge pumps disabled.	AVDD ≥ 2.5v
0x1	Enable charge pump for I/O analog mux and Analog Comparator (AC)	AVDD < 2.5v
---	Reserved
0x3	Enable charge pumps for I/O, AC, ADC Modules 2 & 3
---	Reserved
0x5	Enable charge pumps for I/O, AC, ADC Modules 0 & 1 plus PTC
---	Reserved
0x7	Enable for charge pumps for I/O, AC, ADC Modules 0, 1, 2 & 3 plus PTC

Note:

When AVDD < 2.5v the corresponding appropriate CPEN must be enabled.
User must have previously enabled the charge pump clocks defined in Configuration Register 5, FUCFG5.

Bit 5 – BKUP_VLD MCU Backup Domain Valid Status Bit

Note: Hardware Cleared by Reset and Power Management Unit Whenever Backup power domain is lost. Software (SW) Set by Backup Domain Initialization Code in BOOT ROM when completed.

Value	Description
0	Backup “BKUP” Power Domain has encountered a power loss and contents are not valid.(DEFAULT)
1	Backup “BKUP” Power Domain has not encountered a power loss. Contents are valid.

Bit 4 – SRAM_VLD SRAM Valid Status Bit