26.7.3 Interrupt Flag Status and Clear
Note: Subsequent to an interrupt flag being cleared, the flag must be read back to
verify the clear before exiting the ISR. Failure to do this can result in duplicate
interrupts.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAG |
| Offset: | 0x0008 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ADDVREGRDY2 | ADDVREGRDY1 | ADDVREGRDY0 | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BORVDDUSB1 | BORVDDUSB0 | LVDRDY | LVDET | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 8, 9, 10 – ADDVREGRDYn Additional Regulator n Ready , n = 0 for USB-PHY0, n = 1 for USB-PHY1, and n = 2 for PLL
Set by hardware when the corresponding Additional Regulator is ready and the output voltage is correct.
Write one to clear the corresponding bit.
Bits 5, 6 – BORVDDUSBn Brown-Out detected for a VDD_USB, n = 0,1
Set by hardware when a Brown-Out has been detected on the corresponding VDD_USB.
Write one to clear the corresponding bit.
Bit 1 – LVDRDY Low Voltage Detector Ready
Set by hardware the Low Voltage Detector is ready to operate.
Write one to clear the corresponding bit.
Bit 0 – LVDET Low Voltage Detected
Set by hardware if VDDIO crosses the threshold voltage in a “good” direction according to LVD.DIR.
Write one to clear the corresponding bit.