37.14.2 TX Control Status Register High for Endpoint 1-7
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TXCSRH |
| Offset: | 0x1013 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| AUTOSET | ISO | MODE | DMAREQEN | FRCDATATOG | DMAREQMODE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – AUTOSET Auto Set Control bit
| Value | Description |
|---|---|
| 0 | TXPKTRDY must be set manually for all packet sizes |
| 1 | TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TXPKTRDY will have to be set manually. |
Bit 6 – ISO Isochronous TX Endpoint Enable bit
This bit only has an effect in Device mode. In Host mode, it always returns zero.
| Value | Description |
|---|---|
| 0 | Disables the endpoint for Isochronous transfers and enables it for Bulk or Interrupt transfers. |
| 1 | Enables the endpoint for Isochronous transfers |
Bit 5 – MODE Endpoint Direction Control bit
This bit only has any effect where the same endpoint FIFO is used for both TX and RX transactions.
| Value | Description |
|---|---|
| 0 | Endpoint is RX |
| 1 | Endpoint is TX |
Bit 4 – DMAREQEN Endpoint DMA Request Enable bit
| Value | Description |
|---|---|
| 0 | DMA requests are disabled for this endpoint |
| 1 | DMA requests are enabled for this endpoint |
Bit 3 – FRCDATATOG Force Endpoint Data Toggle Control bit
| Value | Description |
|---|---|
| 0 | No forced behavior |
| 1 | Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. |
Bit 2 – DMAREQMODE Endpoint DMA Request Mode Control bit
This bit must not be cleared either before or in the same cycle as the DMAREQEN bit is cleared.
| Value | Description |
|---|---|
| 0 | DMA Request Mode0 |
| 1 | DMA Request Mode1 |