37.14.3 RX Control Status Register Low for Endpoint 1-7
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | RXCSRL |
| Offset: | 0x1016 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLRDATATOG | SENTSTALL | SENDSTALL | FLUSHFIFO | DATAERROR | OVERRUN | FIFOFULL | RXPKTRDY | ||
| Access | R/W/HC | R/W/HS | R/W | R/W/HC | R/W/HC | R/W/HS | R/W/HC | R/W/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CLRDATATOG Clear Data Toggle Control Bit
| Value | Description |
|---|---|
| 0 | Do not clear the data toggle |
| 1 | Resets the endpoint data toggle to 0 |
Bit 6 – SENTSTALL Stall Handshake Status Bit
| Value | Description |
|---|---|
| 0 | Written by the software to clear this bit |
| 1 | STALL handshake is transmitted |
Bit 5 – SENDSTALL STALL Handshake Control bit (Device Mode)
| Value | Description |
|---|---|
| 0 | Terminate stall condition |
| 1 | Issue a STALL handshake |
Bit 4 – FLUSHFIFO FIFO Flush Control bit
This bit is automatically cleared.
| Value | Description |
|---|---|
| 0 | Normal FIFO operation |
| 1 | Flush the next packet to be read from the endpoint RX FIFO. The FIFO pointer is reset and the RXPKTRDY bit is cleared. This should only be used when RXPKTRDY is set. If the FIFO is double- buffered, FLUSH may need to be set twice to completely clear the FIFO. |
Bit 3 – DATAERROR Data Packet Error Status bit
This bit is cleared when RXPKTRDY is cleared. This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero.
| Value | Description |
|---|---|
| 0 | No data error |
| 1 | The data packet has a CRC or bit-stuff error. |
Bit 2 – OVERRUN Data Overrun Status bit
This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero.
| Value | Description |
|---|---|
| 0 | Written by software to clear this bit |
| 1 | An OUT packet cannot be loaded into the RX FIFO. |
Bit 1 – FIFOFULL FIFO Full Status bit
| Value | Description |
|---|---|
| 0 | The RX FIFO has at least one free space |
| 1 | No more packets can be loaded into the RX FIFO |
Bit 0 – RXPKTRDY Data Packet Reception Status bit
| Value | Description |
|---|---|
| 0 | Written by software to clear this bit when the packet has been unloaded from the RX FIFO. |
| 1 | A data packet has been received. An interrupt is generated. |