37.14.4 RX Control Status Register High for Endpoint 1-7
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | RXCSRH |
| Offset: | 0x1017 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| AUTOCLEAR | ISO | DMAREQENAB | DISNYET | DMAREQMODE | INCOMPRX | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – AUTOCLEAR Automatic Clear Control bit
This bit should not be set for high-bandwidth Isochronous endpoints.
| Value | Description |
|---|---|
| 0 | No automatic clearing of RXPKTRDY |
| 1 | RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the RXFIFO. When packets of less than the maximum packet size are unloaded, RXPKTRDY will have to be cleared manually. When using a DMA to unload the RX FIFO, data is read from the RX FIFO in 4-byte chunks regardless of the RXMAXP. |
Bit 6 – ISO Isochronous Endpoint Control bit (Device Mode)
This bit only has an effect in Device mode. In Host mode, it always returns zero.
| Value | Description |
|---|---|
| 0 | Enable the RX endpoint for Bulk/Interrupt transfers |
| 1 | Enable the RX endpoint for Isochronous transfers |
Bit 5 – DMAREQENAB DMA Request Enable Control bit
| Value | Description |
|---|---|
| 0 | Disable DMA requests for the RX endpoint. |
| 1 | Enable DMA requests for the RX endpoint. |
Bit 4 – DISNYET Disable NYET Handshakes Control/PID Error Status bit (Device mode)
In Bulk/Interrupt transactions, this bit only has any effect in Hi-Speed mode, in which mode it should be set for all Interrupt endpoints.
| Value | Description |
|---|---|
| 0 | Normal operation. |
| 1 | In Bulk/Interrupt transactions, disables the sending of NYET handshakes. All successfully received RX packets are ACKed including at the point at which the FIFO becomes full. |
Bit 3 – DMAREQMODE DMA Request Mode Selection bit
| Value | Description |
|---|---|
| 0 | DMA Request Mode 0 |
| 1 | DMA Request Mode 1 |
Bit 0 – INCOMPRX Incomplete Packet Status bit
| Value | Description |
|---|---|
| 0 |
Written by the software to clear this bit |
| 1 | The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because parts of the data were not received |