37.8.2 USB Configuration Data Register

Table 37-52. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CONFIGDATA
Offset: 0x101F
Reset: 0x0000
Property: Read-Only

Bit 76543210 
 MPRXEMPTXEBIGENDIANHBRXEHBTXEDYNOFIFOSIZINGSOFTCONEUTMIDATAWIDTH 
Access RRRRRRRR 
Reset xx0xxx10 

Bit 7 – MPRXE Automatic Amalgamation Option bit

ValueDescription
0No automatic amalgamation
1Automatic amalgamation of bulk packets is done

Bit 6 – MPTXE Automatic Splitting Option bit

ValueDescription
0No automatic splitting
1Automatic splitting of bulk packets is done

Bit 5 – BIGENDIAN Byte Ordering Option bit

ValueDescription
0Little Endian ordering
1Big Endian ordering

Bit 4 – HBRXE High-Bandwidth RX ISO Option bit

ValueDescription
0No High-bandwidth RX ISO support
1High-bandwidth RX ISO endpoint support is selected

Bit 3 – HBTXE High-Bandwidth TX ISO Option bit

ValueDescription
0No High-bandwidth TX ISO support
1High-bandwidth TX ISO endpoint support is selected

Bit 2 – DYNOFIFOSIZING Dynamic FIFO Sizing Option bit

ValueDescription
0No Dynamic FIFO sizing
1Dynamic FIFO sizing is supported

Bit 1 – SOFTCONE Soft Connect/Disconnect Option bit

ValueDescription
0Soft Connect/Disconnect is not supported
1Soft Connect/Disconnect is supported

Bit 0 – UTMIDATAWIDTH UTMI+ Data Width Option bit

Always '0', indicating 8-bit UTMI+ data width.