37.8.1 Endpoint0 RX Count Register
Count0 is a read-only register that indicates the number of received data bytes in the Endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while RxPktRdy (CSR0.D0) is set.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | COUNT0 |
| Offset: | 0x1018 |
| Reset: | 0x0000 |
| Property: | Read Only |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ENDPOINT0RXCOUNT[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 6:0 – ENDPOINT0RXCOUNT[6:0]
The number of received data bytes in the Endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while the RXPKTRDY bit is set.