11.4.1.7 FUCFG6 - User Configuration Register 6 – FCR.ECCCTRL Configuration

Name: FUCFG6

Offset: 0x0058

• Factory Default: 0x0000_0070
• Value after chip erase: 0x0000_0070

Bits 15-8 SECCNT[7:0] : Single Error Control Configuration Bits

SECCNT is the start value of an internal counter that decrements (by 1 per panel reporting a “single error count”, (i.e., SEC) it’s count value each time an SEC event occurs (including ECC CTL[2:0] bit if in Dynamic ECC Mode). The internal counter stops decrementing at zero. If an SEC error occurs when the internal counter is zero, the SERR flag bit is set.

Bit 6 ECCUNLCK : NVM ECC Mode Control Unlock configuration bits

The ECC mode of the Flash can be locked for the duration of the program lifetime in Flash. When FECCUNLCK is 0, ECCUNLCK is also 0 and the selected ECC mode cannot be changed until Flash is updated. This option prevents undesired changing of the mode. When FECCUNLCK is 1 (the default erased state of the Flash), ECCUNLCK and ECCCTL can be modified.

The read value dictates the unlock state.

Bits 5-4 ECCCTRL[1:0] : NVM ECC Mode Control configuration bits

The field ECCCTL determines how the parity bits are used for Flash reads and writes. The four options, ECC, Dynamic, Dynamic w/o Bus Error and Bypass affect reads and writes differently.

For all ECC modes, writes to the Flash update the Flash ECC Control Bits, CTL[2:0], which store whether ECC or Simple Parity was calculated on the data. The Control Bits exists per Flash word (256-bit data). If the Flash Controller Writes, (FCW), performs a Single Write then the CTL is written with 0b111 (i.e. not changed from the default erase value of the bits) for Parity. If the FCW performs a Quad Write then the CTL is written as 0b000 for ECC. CTL[2:0] must be 0b111 for Single Writes using Simple Parity since all Flash ECC Control Bits (CTL) are not updated with a Single Write. CTL[2:0] is updated for Quad Writes so 0b000 works for selecting ECC.