37.11.2 TX Control Status Register High for Endpoint 1-7

Table 37-66. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: TXCSRH
Offset: 0x1013
Reset: 0x0000
Property: PAC Write-Protection

Bit 76543210 
 AUTOSET MODEDMAREQENABFRCDATATOGDMAREQMODEDATATOGGLEWRENABLEDATATOGGLE 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – AUTOSET Auto Set Control bit

ValueDescription
0TXPKTRDY must be set manually for all packet sizes
1TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TXPKTRDY will have to be set manually.

Bit 5 – MODE Endpoint Direction Control Bit

ValueDescription
0Endpoint is RX
1Endpoint is TX

Bit 4 – DMAREQENAB Endpoint DMA Request Enable bit

ValueDescription
0DMA requests are disabled for this endpoint
1DMA requests are enabled for this endpoint

Bit 3 – FRCDATATOG Force Endpoint Data Toggle Control bit

ValueDescription
0No forced behavior
1Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received.

Bit 2 – DMAREQMODE Endpoint DMA Request Mode Control bit

ValueDescription
0DMA Request Mode0
1DMA Request Mode1

Bit 1 – DATATOGGLEWRENABLE Data Toggle Write Enable bit

ValueDescription
0Disables writing the DATATOGGLE bit
1Enable the current state of the TX Endpoint data toggle (DATATOGGLE) to be written

Bit 0 – DATATOGGLE Data Toggle Control bit

When read, this bit indicates the current state of the TX Endpoint data toggle.

If DATATOGGLEWRENABLE = 1, this bit may be written with the required setting of the data toggle.

If DATATOGGLEWRENABLE = 0, any value written to this bit is ignored.