37.11.3 RX Control Status Register Low for Endpoint 1-7
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | RXCSRL |
| Offset: | 0x1016 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLRDATATOG | RXSTALL | REQPKT | FLUSHFIFO | NAKTIMEOUT | ERROR | FIFOFULL | RXPKTRDY | ||
| Access | R/W/HC | R/W/HS | R/W | R/W/HC | R/W/HS | R/W/HS | R/W/HC | R/W/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CLRDATATOG Clear Data Toggle Control bit
| Value | Description |
|---|---|
| 0 | Leave endpoint data toggle alone |
| 1 | Reset the endpoint data toggle to 0 |
Bit 6 – RXSTALL Stall Handshake Receive Status Bit
| Value | Description |
|---|---|
| 0 | Written by software to clear this bit |
| 1 | STALL handshake is received. An interrupt is generated. |
Bit 5 – REQPKT IN Transaction Request Control bit
This bit is cleared when RXPKTRDY is set.
| Value | Description |
|---|---|
| 0 | No request |
| 1 | Request an IN transaction. |
Bit 4 – FLUSHFIFO FIFO Flush Control bit
This bit is automatically cleared.
| Value | Description |
|---|---|
| 0 | Normal FIFO operation |
| 1 | Flush the next packet to be read from the endpoint RX FIFO. The FIFO pointer is reset and the RXPKTRDY bit is cleared. This should only be used when RXPKTRDY is set. If the FIFO is double- buffered, FLUSH may need to be set twice to completely clear the FIFO. |
Bit 3 – NAKTIMEOUT Data Error/NAK Time-out Status bit (Host mode)
| Value | Description |
|---|---|
| 0 | No data or NAK time-out error |
| 1 | The data packet has a CRC or bit-stuff error. In Bulk mode, the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK limit. |
Bit 2 – ERROR No Data Packet Received Status bit
This bit is only valid when the RX endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero.
| Value | Description |
|---|---|
| 0 | Written by software to clear this bit. |
| 1 | Three attempts have been made to receive a packet and no data packet has been received. An interrupt is generated. |
Bit 1 – FIFOFULL FIFO Full Status bit
| Value | Description |
|---|---|
| 0 | The RX FIFO has at least one free space |
| 1 | No more packets can be loaded into the RX FIFO |
Bit 0 – RXPKTRDY Data Packet Reception Status bit
| Value | Description |
|---|---|
| 0 | Written by software to clear this bit when the packet has been unloaded from the RX FIFO. |
| 1 | A data packet has been received. An interrupt is generated. |