39.7.6.3 Write Cycle

The write cycle time is defined as the total duration of the write cycle; that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is defined as:

NWE CYCLE = NWE SETUP + NWE PULSE + NWE HOLD,

as well as

NWE CYCLE = NCS WR SETUP + NCS WR PULSE + NCS WR HOLD

All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Host Clock cycles. The NWE CYCLE field is common to both the NWE and NCS signals, thus the timing period is of the same duration.

NWE CYCLE, NWE SETUP, and NWE PULSE implicitly define the NWE HOLD value as:

NWE HOLD = NWE CYCLE - NWE SETUP - NWE PULSE

NWE CYCLE, NCS WR SETUP, and NCS WR PULSE implicitly define the NCS WR HOLD value as:

NCS WR HOLD = NWE CYCLE - NCS WR SETUP - NCS WR PULSE