27.7.2 Reference Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | REFCTRL |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | Write-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REFCOMP | REFSEL[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 7 – REFCOMP Reference Buffer Offset Compensation Enable
The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference.
| Value | Description |
|---|---|
| 0 | Reference buffer offset compensation is disabled. |
| 1 | Reference buffer offset compensation is enabled. |
Bits 3:0 – REFSEL[3:0] Reference Selection
These bits select the reference for the ADC.
| REFSEL[3:0] | Name | Description |
|---|---|---|
| 0x0 | INT1V | 1.0V voltage reference |
| 0x1 | INTVCC0 | 1/1.48 AVDD |
| 0x2 | INTVCC1 | 1/2 AVDD (only for AVDD > 2.0V) |
| 0x3 | VREFA | External reference |
| 0x4 | VREFB | External reference |
| 0x5-0xF | Reserved |
Note: INT1V is the buffered internal
reference of 1.0V, derived from the internal 1.1V bandgap reference.