27.7.3 Average Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | AVGCTRL |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | Write-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADJRES[2:0] | SAMPLENUM[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 6:4 – ADJRES[2:0] Adjusting Result / Division Coefficient
These bits define the division coefficient in 2n steps.
Bits 3:0 – SAMPLENUM[3:0] Number of Samples to be Collected
These bits define how many samples should be added together.The result will be available in the Result register (RESULT). Note: if the result width increases, CTRLB.RESSEL must be changed.
| SAMPLENUM[3:0] | Name | Description |
|---|---|---|
| 0x0 | 1 | 1 sample |
| 0x1 | 2 | 2 samples |
| 0x2 | 4 | 4 samples |
| 0x3 | 8 | 8 samples |
| 0x4 | 16 | 16 samples |
| 0x5 | 32 | 32 samples |
| 0x6 | 64 | 64 samples |
| 0x7 | 128 | 128 samples |
| 0x8 | 256 | 256 samples |
| 0x9 | 512 | 512 samples |
| 0xA | 1024 | 1024 samples |
| 0xB-0xF | Reserved |