1.9.2 MIPI TX

The MIPI LP (Low Power) signals must be connected to a 1.2V GPIO/HSIO Bank supply and High-speed signals must be connected to a 2.5V GPIO Bank supply. Select the High Speed (HS) and Low Power (LP) pins in adjacent pins to minimize the LP stub. The HS data and clock signals must be in one DDR_Lane. For more information about DDR_Lane information, see the Package Pin Assignment Tables (PPAT).

The MIPI TX standard is implemented by using the resistor divider network for LP and HS signals, as shown in the following figure. The resistor values mentioned in the following provide a throughput upto of 1 Gbps.

Figure 1-10. MIPI TX Connections
Important: Run the PDC verification in the Libero tool before moving to layout. For more information about MIPI RX electrical characteristics, see PolarFire FPGA Datasheet .

For information about the MIPI layout guidelines, see MIPI.