2.1.3 Transceiver Interface Configurator

The Transceiver Interface Configurator is used to build the transceiver based on protocol requirements. The user selects the number of lanes, data rate, and protocol-specific settings.

To initiate the Transceiver Interface Configurator, perform the following steps:

  1. Access the Transceiver Interface module under Features from the Catalog window, as shown in the following figure.
    Figure 2-17. Transceiver Interface Selection From Catalog
  2. Double-click each PF_XCVR block in the catalog to launch the configurator. A GUI allows the option to select the related XCVR properties.
    Figure 2-18. Transceiver Interface Configuration GUI

    The following tables list Transceiver Interface options.

    Table 2-5. Transceiver Interface General Settings
    GeneralOptionsDefaultDetails
    Number of lanes1 to 41
    Transceiver modeTx and Rx (Full Duplex)Tx and Rx (Full Duplex)See Transceiver Modes for more information.
    Tx Only
    Rx Only
    Tx and Rx (Independent)
    Enhanced Receiver ManagementEnable/DisabledEnabledIncludes the enhanced receiver management solution when checkbox is checked (See Enhanced Receiver Management).
    Receiver CalibrationNone (CDR), 
On-Demand,
On-Demand & First Lock, and None (DFE),

    Incrementally Recalibrate Data Eye and Incrementally Recalibrate DFE Coefficients

    		On-Demand & First LockSee Receiver.
    Table 2-6. Transceiver Interface PMA Settings
    PMA SettingsOptionsDefaultDetails
    Tx data rate250 – 12700 Mbps5000 Mbps10312.5 Mbps (STD maximum)
    TX clock division factor1, 2, 4, 8, and 111—
    TXPLL base data rateComputed1——
    TX PLL bit clock frequencyComputed——
    RX Data rate250 Mbps – 12700 Mbps5000 Mbps10312.5 Mbps (STD maximum)
    RX CDR lock modeLock to reference, Lock to data, Burst Mode Receiver2, lock to data with 2x gain3Lock to data—
    RX CDR reference clock sourceDedicated and fabricDedicated—
    RX CDR reference clock frequency4Based on transceiver data rate——
    RX JA Clock FrequencyCalculated based on configuration——
    Note:
    1. Enter the transceiver data rate (lane rate), and the TX clock division factor in the XCVR UI. Based on these settings, the TX_PLL base data rate is calculated. The TX_BIT_CLK frequency is half of the TX_PLL base data rate. The TX_PLL base data rate must be entered under the desired output clock option of the PF_TX_PLL block. The PF_TX_PLL generates the BIT_CLK output (connected to the TX_BIT_CLK_0/1 input of PF_XCVR).
    2. When Burst Mode Receiver (BMR) is selected, LANE_X_CDR_LOCKMODE[1:0] port is exposed.
    3. Default Gain, slower CDR lock time, lower jitter tolerance 2x Gain, faster CDR lock time, higher jitter.
    4. This input frequency is given by the user to support the integer feedback divider of the receiver PLL. From the drop-down, enter a CDR reference clock frequency (MHz) value equal to the reference clock used to the Receiver PLL. The computation derives the feedback divider used to clock the receiver data path.
    Table 2-7. Transceiver Interface PCS Settings
    PCS SettingsOptionsDefaultDetails
    PCS-fabric interface width8, 10, 16, 20, 32, 40, 64, and 80140—
    FPGA interface frequency2Computed——
    PMA ModeEnable CDR Bit-slip portEnable—
    8b10b encoding/decodingNone——
    64b6xb gear box64b66b

    64b67b

    		64b66bIf 64b6xb mode is enabled, then PCS-Fabric interface width must be 32- or 64-bit.
    64b66b gear box3Enable disparityDisabledEnabled for 64b67b
    Enable scrambler/de-scramblerDisabled—
    Enable BER monitor state machineDisabled—
    Enable 32 bits data widthDisabled—
    64b67b gear box3Enable BER monitor state machineDisabledEnable 32 bits data width
    Enable DisparityDisabledCannot be enabled for 64b66b
    Enable Scrambler/de-scramblerDisabled—
    Enable 32 bits data widthDisabled—
    Soft PIPE interfacePCIe Gen1 (2.5 Gbps) 
PCIe Gen2 (5.0 Gbps)PCIe Gen1 (2.5 Gbps)—
    Note:
    1. Dependent on PCS settings.
    2. TX_CLK_G/R frequency = RX_CLK_G/R frequency = FPGA Interface frequency = data rate/(PMA-PCS width × PCS Gearing).
    3. When 64b6xb Gear Box is enabled, the Enable Disparity, Enable BER monitor state machine, Enable Scrambler/Descrambler, and Enable 32 bits data width options can be enabled or disabled independently for both 64b66b and 64b67b.
    Table 2-8. Clocks and Resets
    Interface OptionsOptionsDefaultDetails
    Interface clockUse as PLL reference clockDisabledWhen Use as PLL reference clock is selected, this exposes additional ports that permit connection to the PLL REFCLKs.

    LANEn_TX_CLK_TO_PLL_REFCLK

    LANEn_RX_CLK_TO_PLL_REFCLK

    This allow designs that require gearing other than 2:1 with wider fabric interfaces and use dedicated routing to the PLL. This is used in place of CLKDIV, which does not have the dedicated routing to PLL.

    TX clock 2Global, Regional, 
Regional (Deterministic), Global SharedRegionalSee Table 1-16
    RX clock 2Global, Regional, 
Regional (Deterministic), Global Shared, and NARegionalNA option must be selected when the PCS is configured in Soft PIPE mode (PCIe). See Table 1-16
    Interface ResetsPMA Reset1TX and RX—
    PCS Reset1Tx Only, Rx Only, Tx and RxRX Only – only RX side can be reset from the fabric.

    TX Only – only TX side can be reset from the fabric.

    TX and RX – both RX and TX sides can be reset from the fabric.

    Optional PortsEnable/Disable—TX_BYPASS port/TX_ELEC_IDLE port.

    See Table 1-10 or Table 1-12.

    RX_READY_CDR and RX_VAL_CDR ports.

    See Enhanced Receiver Management.

    JA_CLK port. See Jitter Attenuator.
    Dynamic ReconfigurationEnable Dynamic Reconfiguration Interface (DRI)Disabled—
    Note:
    1. The minimum pulse width required is 16 clock cycles.
    2. To toggle TX clock and RX clock, an active pulse is provided on PCS Reset and PMA Reset.

    Preset configurations are available within the Transceiver Interface Configurator to speed up the transceiver configuration. Factory provided presets are available with the Libero release. Additionally, customized presets can be saved. See Transceiver Modes for more information.

  3. Select Number of lanes from 1 to 4 in the general settings configuration.
  4. Enter the Transceiver data rate and select one of the TX clock division factors. The TX PLL base data rate is calculated in the GUI. The calculated TX PLL base data rate must be entered under the desired output clock option inside the PF_TX_PLL configurator. LANE#_TX_PLL_REF_CLK_#, LANE#_TX_BIT_CLK_0, and LANE#_TX_PLL_LOCK_# are included in CLKS_FROM_TXPLL_# BIF (bus interface). This connection is required between the TXPLL and Transceiver Interface.
  5. Select the desired CDR reference clock mode and CDR reference clock frequency from the drop-down list based on the application.
    Important: CDR reference clock frequency drop-down list is populated with valid frequencies based on the data rate.
  6. Select the CDR reference clock source based on the design requirements. The dedicated clock adds a dedicated CDR_REF_CLK port whereas the fabric port only includes a port that can be connected to the fabric resources. The dedicated CDR_REF_CLK_0/1 port must be connected to the REF_CLK or REF_CLK_0/1 output of the PF_XCVR_REF_CLK block.
  7. Select PCS-Fabric interface width from the GUI. This selection computes the FPGA interface frequency. The FPGA interface frequency is calculated based on the transceiver data rate, 
PCS-Fabric width, and the PCS settings/mode.
  8. Click the GUI radio button to select the desired PCS mode. See Transceiver PCS Interface Modes for more information on PCS mode.
  9. Select the desired interface clock options in the Interface Options GUI. See PCS/FPGA Fabric Interface.
  10. For PMA Only modes - CDR Bit-slip, select the Enable CDR Bit-slip port to add the LANE#_RX_SLIP pin.
    Figure 2-19. PMA Mode—Enable CDR Bit-Slip Port
    Figure 2-20. XCVR Component With CDR Bit-Slip Port Enabled
    Important: For information about RX_SLIP, see Bit Slip.
    Figure 2-21. XCVR Component With BMR Port Enabled
    Important: For information about CDR_LOCKMODE pins, see burst mode receiver in CDR Options.
  11. Select the Enable Dynamic Reconfiguration to add the LANE#_DRI_SLAVE pins. See Dynamic Reconfiguration Interface for usage details.
    Figure 2-22. XCVR Component With DRI Port Enabled
  12. After making all of the selections in the Transceiver Interface Configurator, click OK.

When the transceiver interface configuration is complete, a PF_XCVR macro is generated by the Libero Software. The macro includes the ports based on the configuration. Figure   7 to Figure   11 shows sample PCS macros. The PF_XCVR macro is instantiated into the user design to customize the connectivity of the application.

Figure 2-23. Transceiver with ERM Example SmartDesign Component
Figure 2-24. PMA Only PCS Example SmartDesign Component
Figure 2-25. 8b10b PCS Example SmartDesign Component
Figure 2-26. 64b66b PCS Example SmartDesign Component
Figure 2-27. Soft PIPE PCS Example SmartDesign Component

After building the PF_XCVR, PF_TX_PLL, and PF_XCVR_REF_CLK cores, the transceiver subsystem must be connected together in the SmartDesign canvas. Typically, the REF_CLK and/or FAB_REF_CLK outputs of the PF_XCVR_REF_CLK are connected to the respective inputs of the PF_XCVR and the input REF_CLK of the PF_TX_PLL. LANE#_TX_PLL_REF_CLK_#, LANE#_TX_BIT_CLK_0, and LANE#_TX_PLL_LOCK_# are included in CLKS_FROM_TXPLL_# BIF (bus interface). This connection is required between the TXPLL and transceiver interface. The SmartDesign component must then be generated.

Figure 2-28. Completed Transceiver Subsystem
Figure 2-29. Completed Transceiver Subsystem with ERM

See the port list tables in Transceiver PCS Interface Modes for complete pin descriptions generated with the Transceiver Configurator.