2.5.4 Soft-Start, Start-Up Sequence Step Assignment and Sequence Step Delay (t1, t2, t3) Programming Bits

For each regulator, the SSR[1:0] bits define the Soft-Start Rate in terms of time duration of each voltage step (tramp).

Table 2-7. Soft-Start Rate Bits SSR[1:0]
SSR[1:0]2 MHz Clock Divisiontramp (μs)Buck2, 3, 4 25 mV Step - Average Ramp Rate (V/ms)Buck1, LDO1,2 50 mV Step - Average Ramp Rate (V/ms)COUT (μF)Average COUT Capacitor Current (mA) - 25 mV stepAverage COUT Capacitor Current (mA) - 50 mV step
001683.1256.2502269138
0132161.5633.125223469
1048241.0422.083222346
1164320.7811.563221734

The SEQ[1:0] bits assign each regulator at a determined step in the start-up sequence. Assignment SEQ[1:0] = 00 (first sequence step) means the regulator is started upon a valid start-up event.

However, each regulator is allowed to turn ON at its assigned start-up sequence step only if its SEQEN bit is set. If SEQEN = 0, the regulator will NOT turn on, and it will be disregarded in the sequence generation and nRSTO assertion algorithm.

Upon exit of HIBERNATE mode, all regulators (typically Buck2 and LDO2) which were already ON in HIBERNATE mode and have SEQEN = 1 will stay ON continuously throughout the execution of the start-up sequence.

Table 2-8. Start-Up Sequence Step Assignment Bits SEQ[1:0]
SEQ[1:0]Start-Up Sequence Step
001
012
103
113
Table 2-9. Sequence Step Delay Bits DELAY[2:0]
DELAY[2:0]Delay (ms)
0000
0010.5
0101
0112
1004
1018
11012
11116

For each regulator these bits program the delay (t1 to t3) from the completion of the previous sequence step to the beginning of its turn-on (beginning of Soft-Start, if SEQEN = 1).

For regulators assigned to the first sequence step (SEQ[1:0] = 00) i.e. starting at t1, this is the additional delay after the device wake-up time since the start-up event (e.g. PWRHLD low-to-high).

This way, by setting a DELAY[2:0] = 001 or higher, it is possible to define a de-bouncing time of the EN event.