2.4.4 Typical Power-Down Sequence and Timing

The power-down (shutdown) sequence can be initiated in two ways:

  1. Initiated by the MPU, by de-asserting PWRHLD (LPM being already LOW or de-asserted simultaneously). This is the normal method, which assumes that the MCP16503 was in any operating state (i.e. was outside the start-up sequence).
  2. Initiated externally by pulling down EN, after t8 (enable timeout delay) + t9 (enable interrupt assertion timeout delay, if no action is taken by the MPU within t9).

After PWRHLD has been de-asserted or t9 has reached EOC, nRSTO will immediately be asserted LOW by the MCP16503. After that, the turn-off of all Buck channels can take place with no delay, in any order.

The turn-off of each channel also activates the active discharge (if enabled) on the same channel.

The timing diagram shown in Figure 2-7 shows the typical sequence for the first case:

Figure 2-7. Power-Down (Shutdown) Sequence Timing Diagram

Where:

  • t5 = setup time, LPM = "0" to PWRHLD = "0": min. 0 ms (internal filtering applies)
  • t6 = delay from PWRHLD de-asserted to nRSTO asserted: min. 0 ms, max 10 ms (not a strict requirement)
  • t7 = dela
  • y from nRSTO asserted to first VOUTX turn-off: min. 0 ms, max 10 ms (not a strict requirement)

 

The following timing diagram in Figure 2-8 (shows the typical sequence for the second case):

Figure 2-8. EN Shutdown Sequence Timing Diagram

Where:

  • t8 = enable (EN = 0) timeout delay (default ENTO[1:0] = 01 i.e. 4s)
  • t9 = enable interrupt assertion timeout delay (default ENINTTO[1:0] = 01 i.e. 0.5s)
  • t7 = delay from nRSTO asserted to first VOUTX turn-off: min. 0 ms, max 10 ms (not a strict requirement)

If EN is pulled down continuously for the entire t8 duration, an interrupt will be asserted (nINTO goes LOW).

The interrupt assertion of this particular type of interrupt also set ENINT (Enable Interrupt) bit in register STS-SYS 0x04h (STS-SYS[5]). This interrupt is not maskable.

If the MPU reads register STS-SYS before t9 expires, bit ENINT is acquired and Reset-on-Read. Then, the MPU can decide either to continue operating, or to initiate a shutdown by de-asserting PWRHLD.

Once the ENINT bit is cleared by the MPU upon reading register STS-SYS, MCP16503 de-asserts the interrupt, stops the t9 counting, resets both t8 (which reached EOC) and t9, and if the condition (EN = 0) is no longer active, it does not take any countermeasure and continues operating.

If the MPU does NOT read STS-SYS register before t9 expires, then MCP16503 will go into shutdown autonomously. A new EN = 1 start-up event will be needed to retrieve PMIC operation.

If t9 expires when MCP16503 is in “Start-Up wait” mode, the 100 ms timer shall be terminated and MCP16503 shall move to “OFF” mode.

If the MPU reads register STS-SYS before the t9 expires and decides to do nothing, but the enable condition is still present, the t8 (and then t9) counter will start again. This way, the long-press condition can be extended indefinitely by simply reading register STS-SYS each time nINTO is asserted.

The enable timeout delay t8 is user programmable with bits ENTO[1:0] from 0s to 8s (0s – 2s – 4s – 8s).

The enable interrupt assertion timeout delay t9 is user-programmable with bits ENINTTO[1:0] from 100 ms to 2s (100 ms – 500 ms –1s – 2s).