2.4.6 Typical HIBERNATE Sequences and Timing

The HIBERNATE mode entering sequence is similar to the Power-Down, with the only difference that LPM will be asserted HIGH by the MPU before de-assertion of PWRHLD, or at least at the same time PWRHLD is de-asserted (due to internal filtering, the setup time t5 can be as low as 0 μs). The VOUT2 rail (and/or other rails which are defined ON in HIBERNATE mode) will remain active, while VOUT1, VOUT3 and VOUT4 will be immediately disabled. In HIBERNATE mode, the DDRx/LPDDRx will typically be in backup self-refresh mode (BSR).

The following timing diagram of Figure 2-9 shows the typical HIBERNATE sequence for a device that keeps only VOUT2 ON during HIBERNATE mode:

Figure 2-9. Entering HIBERNATE Mode Timing Diagram

Where:

  • t5 = setup time, LPM = "1" to PWRHLD = "0": min. 0 μs (internal filtering applies)
  • t6 = delay from PWRHLD de-asserted to nRSTO asserted: min. 0 μs, max 10 μs (not a strict requirement)
  • t7 = delay from nRSTO asserted to first VOUTX turn-off: min. 0 μs, max 10 μs (not a strict requirement)

From the HIBERNATE state, the system can:

  1. Move to OFF state (if also LPM goes LOW, the VOUT2 can be immediately turned OFF), or
  2. initiate another start-up sequence (except for Buck2 which is already active and has its SEQEN = 1) by a low-to-high transition of PWRHLD.

The timing diagram of a start-up sequence from HIBERNATE mode is shown in Figure 2-10. After the assertion of PWRHLD, the MPU may de-assert LPM at any time. Due to internal filtering, simultaneous transition of LPM and PWRHLD is allowed (hold time t5 can be 0 μs).

Depending on the time at which LPM is de-asserted, the MCP16503 may transition through the Low-Power state or not.

Figure 2-10. Start-Up Sequence exiting HIBERNATE Mode Timing Diagram

Where:

  • t1 = delay from PWRHLD asserted to first supply VOUT1 starting (SEQ[1:0] = 00, default DELAY[2:0] = 001 i.e. 0.5 ms)
  • t3 = time from VOUT1 established to VOUT3, VOUT4 starting (SEQ[1:0] = 10, default DELAY[2:0] = 100 i.e. 4 ms)
  • t4 = time from VOUT3, VOUT4 established to nRSTO de-assertion (default v[2:0] = 100 i.e. 16 ms)
  • t5 = minimum hold time, PWRHLD = ”1” to LPM = ”0”: min. 0 μs (internal filtering applies)
Note: Upon exiting HIBERNATE mode, Buck2 is not part of the sequence, because it is already ON (being in Auto PFM mode) and its SEQEN = 1.

However, also depending on the instant at which the MPU de-asserts LPM, it can toggle to FPWM mode at the time nRSTO is asserted HIGH.

Similar to Buck2, any other regulator which is defined ON in the HIBERNATE state, and has its bit SEQEN = 1, will NOT be turned OFF when exiting the HIBERNATE state for a new start-up sequence.

If the regulator is defined ON in the HIBERNATE state, but its bit SEQEN = 0, it will be turned OFF as soon as the new start-up sequence is initiated.

In conclusion, for a regulator to stay ON continuously from the HIBERNATE state throughout the new start-up sequence, two conditions must be satisfied:

  1. The regulator is set ON in the HIBERNATE state;
  2. The SEQEN bit is set to 1.