2.4.2 Power-up Sequence Programming and Flowchart

The power-up sequence management is flexible enough to accommodate other Power-Up sequences than the typical one.

The start-up sequence is divided into three steps, and each regulator (Bucks and LDOs) is included in the start-up sequence ONLY if its SEQEN bit is set. Each regulator is then assigned to a specific sequence step:

  1. (SEQ[1:0] = 00): enabled (bit SEQEN = 1) regulator(s) are started after a delay (t1 ) since the start-up event. If the start-up event is no longer valid at the instant t1 expires, the start-up sequence is aborted before the first regulator is started;
  2. (SEQ[1:0] = 01): enabled (bit SEQEN = 1) regulator(s) are started after a delay (t2 ) since the completion of the sequence step 1 (all regulators enabled at step 1 have been powered up correctly);
  3. (SEQ[1:0] = 1x): enabled (bit SEQEN = 1) regulator(s) are started after a delay (t3 ) since the completion of the sequence step 2 (all regulators enabled at steps 1 and 2 have been powered up correctly).

Note that if more than one regulator is assigned to power up at a given sequence step, their DELAY[2:0] bits might still be different. Therefore, they might initiate their Soft-Start ramps at different times, even if they are assigned to the same sequence step. This is useful to reduce input inrush currents at start-up and allow for even more sequencing flexibility.

The subsequent assertion of nRSTO is determined only by the status of all regulators that have been turned ON during the Power-Up Sequence (SEQEN = 1). Their status is checked before starting counter t4 and again checked at the expiration of t4 to have nRSTO asserted.

The status of the regulators that have NOT been turned ON during the Power-Up sequence (SEQEN = 0) is not taken into account for the assertion of nRSTO.

After the completion of the Power-Up sequence, i.e. at the time instant nRSTO is asserted high, the MCP16503 will enter the Power Modes state machine operation defined by LPM, HPM and PWRHLD signals and the content of registers 0x10-0x13, 0x20-0x23, 0x30-0x33, 0x40-0x43, 0x50-0x53, 0x60-0x63 applies.

Note that there might be a conflict between the enable status of regulator(s) which have been powered-up (SEQEN = 1) or left OFF (SEQEN = 0) during the start-up sequence, and their EN bit (ON or OFF state) in the power modes states (i.e. bit 7 of registers 0x10-0x13, and so on).

For example, LDO2 might not have been enabled to turn-on during the Power-Up sequence (SEQEN = 0), but it is defined as ON in the power modes definition registers 0x60-0x63.

In that case, the power modes definition of register 0x60-0x63 prevails as soon as the Power-Up sequence is completed. So LDO2 will be turned ON immediately after nRSTO has been asserted high.

Some regulators which are supposed to turn-ON in the Power-up sequence may fail to power-up correctly.

In this case, the sequencing engine adds a 32 ms wait time to allow the affected regulators to recover. After the expiration of the 32 ms period, if the affected regulators have still not recovered, the STRT_CNT counter is incremented.

Once the MCP16503 detects 5 invalid start-up attempts, the STRTF flag is set. This flag is automatically cleared when EN = 0 is detected, when the IC enters OFF mode, after a power cycle, or upon any successful start-up. The device will remain in OFF mode until the counter is reset.

The start-up sequence flowchart is described in the following Figure 2-6.

Figure 2-6. Start-Up Sequence Flowchart