5.5.3 Overcurrent Protection (Buck Channels)
The overcurrent protection consists of a cycle-by-cycle, high-side current limit with digital filtering, followed by Hiccup for protection against short-circuits conditions.
The cycle-by-cycle, high-side current limit includes frequency fold-back. Because of Leading-Edge-Blanking in peak-current-mode control, frequency fold-back (with a factor = 4) is used to allow more time for inductor discharge and prevent current runaway in deep overload condition.
Frequency fold-back operation is entered when:
- A high-side current limit event has been detected; and
- The feedback voltage is less than 500 mV (typical).
Cycle-by-cycle overcurrent protection with frequency fold-back is always active and it is the first current limit protection mechanism.
The second current limit mechanism is Hiccup mode protection, which is by default always enabled, including during the Soft-Start ramp and DVS transitions.
Since the hiccup mode protection is also active during Soft-Start, there will be a limitation on the maximum simultaneous DC and capacitive loading to ensure that the hiccup mode protection will not be engaged during the Soft-Start ramp. This is further explained in section PWM Mode Negative Current Limit Protection (Buck Channels).
Hiccup is invoked based on digital counting of high-side overcurrent (HS OC) events, regardless of the frequency at which they take place (full switching frequency or fold-back switching frequency).
Each time the overcurrent protection detects a high-side current limit event, the current ON time is terminated and a HS OC Event counter is incremented. The length of the counter is 4-bits.
If the counter reaches its EOC, while the instantaneous value of POK signal is still low, the buck converter is turned OFF (both High-side and Low-Side transistors are turned OFF) and Hiccup mode protection is triggered.
The intervention of Hiccup on any of the Buck channels can have two different behaviors, depending on the HCPEN bit value of the channel affected by overcurrent conditions. The HCPEN bit is user-accessible through I2C.
If HCPEN = 0, the intervention of Hiccup will immediately terminate the power delivery on all channels, including LDOs. At the same time, nRSTO will be asserted low. If the corresponding masking bit is cleared, nINTO will also be asserted low.
After a 100 ms delay, the MCP16503 will automatically attempt a new start-up sequence, without the need of an external start condition (e.g.from PWRHLD).
If HCPEN = 1, the intervention of Hiccup only affects the responsible Buck channel. All other channels will continue to operate normally. If the affected channel is part of the Power-Up sequence, nRSTO will be asserted low, and if the corresponding masking bit is cleared, nINTO will also be asserted low.
The affected channel will be kept OFF for a certain hiccup time (tHICCUP), which corresponds to 3x Soft-Start time on that channel, and after the hiccup time a new Soft-Start is attempted.
If the short-circuit condition is removed and the affected channel resumes normal operation (POK returns High), nRSTO will be asserted high after the programmed reset delay (t4).
The HS OC event counter is reset only after 15 consecutive HS turn-on pulses without any overcurrent event. This counting is done by the RESET counter.
Note that all counting is switching-event based, so it is not relevant if the switching takes place at fsw or at fsw/4 (i.e. in frequency fold-back).
The hiccup flowchart is detailed below. The overcurrent condition of each Buck is also reported through I2C.