17.1.1 Overview

While Libero SoC provides a fully integrated end-to-end design environment to develop SoC and FPGA designs, it also provides the flexibility to run synthesis and simulation with third-party tools outside the Libero SoC environment. However, some design steps must remain within the Libero SoC environment.

The following table lists the major steps in the FPGA design flow and indicates the steps for which Libero SoC must be used.
Table 17-2. FPGA Design Flow
Design Flow Step Must Use Libero Description
Design Entry: HDL No Use third-party HDL editor/checker tool outside Libero® SoC if desired.
Design Entry: Configurators Yes Create first Libero project for IP catalog core component generation.
Automatic PDC/SDC constraint generation No

Derived constraints need all HDL files and a derive_constraints utility when performed outside of Libero SoC, as described in 17.1.9 Appendix C—Derive Constraints.
Simulation No Use third-party tool outside Libero SoC, if

desired. Requires download of pre-compiled simulation libraries for target device, target simulator, and target Libero version used for backend implementation.
Synthesis No Use third-party tool outside Libero SoC if desired.
Design Implementation: Manage Constraints, Compile Netlist, Place-and-Route (see 17.1.1 Overview) Yes Create second Libero project for the backend implementation.
Timing and Power Verification Yes Stay in second Libero project.
Configure Design Initialization Data and Memories Yes Use this tool to manage different types of memories and design initialization in the device. Stay in second project.
Programming File Generation Yes Stay in second project.
Important: You must download precompiled libraries listed under the Compiled Simulation Libraries for PolarFire section on the Libero SoC Documentation page to use a third-party simulator.
In a CPLD/pure Fabric FPGA flow, enter your design using HDL or schematic entry and pass that directly to the synthesis tools. The flow is still supported. PolarFire and PolarFire SoC FPGAs have significant proprietary hard IP blocks requiring the use of configuration cores (SgCores) from the Libero SoC IP catalog. Special handling is required for any blocks that comprise SoC functionality:
  • PolarFire
    • PF_UPROM
    • PF_SYSTEM_SERVICES
    • PF_CCC
    • PF CLK DIV
    • PF_CRYPTO
    • PF_DRI
    • PF_INIT_MONITOR
    • PF_NGMUX
    • PF_OSC
    • RAMs (TPSRAM, DPSRAM, URAM)
    • PF_SRAM_AHBL_AXI
    • PF_XCVR_ERM
    • PF_XCVR_REF_CLK
    • PF_TX_PLL
    • PF_PCIE
    • PF_IO
    • PF_IOD_CDR
    • PF_IOD_CDR_CCC
    • PF_IOD_GENERIC_RX
    • PF_IOD_GENERIC_TX
    • PF_IOD_GENERIC_TX_CCC
    • PF_RGMII_TO_GMII
    • PF_IOD_OCTAL_DDR
    • PF_DDR3
    • PF_DDR4
    • PF_LPDDR3
    • PF_QDR
    • PF_CORESMARTBERT
    • PF_TAMPER
    • PF_TVS, and so on.

    In addition to the preceding listed SgCores, there are many DirectCore soft IPs available for PolarFire and PolarFire SoC device families in the Libero SoC Catalog that use the FPGA fabric resources.

    For design entry, if you use any one of the preceding components, you must use Libero SoC for part of the design entry (17.1.2 Component Configuration), but you can continue the rest of your Design Entry (HDL entry, and so on) outside of Libero. To manage the FPGA design flow outside of Libero, follow the steps provided in the rest of this guide.