16.2.6 RAM1K18

The RAM1K18 block contains 18,432 memory bits and is a true dual-port memory. It can also be configured in two-port mode. All read/write operations to the RAM1K18 memory are synchronous. To improve the read data delay, an optional pipeline register at the output is available. A feed-through write mode is also available to enable immediate access to the write data. The RAM1K18 memory has two data ports, which can be independently configured in any combination as follows:

  1. Dual-Port RAM with the following configurations:
    • 1Kx18, 1Kx16
    • 2Kx9, 2Kx8
    • 4Kx4
    • 8Kx2
    • 16Kx1
  2. Two-Port RAM with the following configurations:
    • 512x36, 512x32
    • 1Kx18, 1Kx16
    • 2Kx9, 2Kx8
    • 4Kx4
    • 8Kx2
    • 16Kx1

The main features of the RAM1K18 memory block are as follows:

  • It has 18,432 bits.
  • It provides two independent data ports A and B.
  • It has a true dual-port mode, for which both ports have word widths less than or equal to 18 bits.
  • In true dual-port mode, each port can be independently configured to any of the following depth/width: 1Kx18, 1Kx16, 2Kx9, 2Kx8, 4Kx4, 8Kx2, and 16Kx1.
  • The widths of each port can be different, but one needs to be a multiple of the other. There are 29 unique combinations of true dual-port aspect ratios:
    • 1Kx18/1Kx18, 1Kx18/2Kx9
    • 1Kx16/1Kx16, 1Kx16/2Kx8, 1Kx16/4Kx4, 1Kx16/8Kx2, 1Kx16/16Kx1
    • 2Kx9/1Kx18, 2Kx9/2Kx9
    • 2Kx8/1Kx16, 2Kx8/2Kx8, 2Kx8/4Kx4, 2Kx8/8Kx2, 2Kx8/16Kx1
    • 4Kx4/1Kx16, 4Kx4/2Kx8, 4Kx4/4Kx4, 4Kx4/8Kx2, 4Kx4/16Kx1
    • 8Kx2/1Kx16, 8Kx2/2Kx8, 8Kx2/4Kx4, 8Kx2/8Kx2, 8Kx2/16Kx1
    • 16Kx1/1Kx16, 16Kx1/2Kx8, 16Kx1/4Kx4, 16Kx1/8Kx2, 16Kx1/16Kx1
  • RAM1K18 also has a two-port mode. In this case, Port A becomes the read port and Port B becomes the write port.
  • In two-port mode, each port can be independently configured to any of the following depth/width: 512x36, 512x32, 1Kx18, 1Kx16, 2Kx9, 2Kx8, 4Kx4, 8Kx2 and 16Kx1.
  • The widths of each port can be different, but one needs to be a multiple of the other. There are 45 unique combinations of two-port aspect ratios:
    • 512x36/512x36, 512x36/1Kx18, 512x36/2Kx9
    • 512x32/512x32, 512x32/1Kx16, 512x32/2Kx8, 512x32/4Kx4, 512x32/8Kx2, 512x32/16Kx1
    • 1Kx18/512x36, 1Kx18/1Kx18, 1Kx18/2Kx9
    • 1Kx16/512x32, 1Kx16/1Kx16, 1Kx16/2Kx8, 1Kx16/4Kx4, 1Kx16/8Kx2, 1Kx16/16Kx1
    • 2Kx9/512x36, 2Kx9/1Kx18, 2Kx9/2Kx9
    • 2Kx8/512x32, 2Kx8/1Kx16, 2Kx8/2Kx8, 2Kx8/4Kx4, 2Kx8/8Kx2, 2Kx8/16Kx1
    • 4Kx4/512x32, 4Kx4/1Kx16, 4Kx4/2Kx8, 4Kx4/4Kx4, 4Kx4/8Kx2, 4Kx4/16Kx1
    • 8Kx2/512x32, 8Kx2/1Kx16, 8Kx2/2Kx8, 8Kx2/4Kx4, 8Kx2/8Kx2, 8Kx2/16Kx1
    • 16Kx1/512x32, 16Kx1/1Kx16, 16Kx1/2Kx8, 16Kx1/4Kx4, 16Kx1/8Kx2, 16Kx1/16Kx1
  • RAM1K18 performs synchronous operation for setting up the address as well as writing and reading the data. The address, data, block port select, and write enable inputs are registered.
  • An optional pipeline register with a separate enable, synchronous-reset, and asynchronous-reset is available at the read data port to improve the clock-to-out delay.
  • There is an independent clock for each port. The memory is triggered at the rising edge of the clock.
  • The true dual-port mode supports an optional feed-through write mode, where the write data also appears on the corresponding read data port.
  • Read from both ports at the same location is allowed.
  • Read and write on the same location at the same time results in unknown data to be read. There is no collision prevention or detection. However, correct data are expected to be written into the memory.
The following simplified block diagram illustrates the two independent data ports, the pipeline registers, and the feed-through multiplexors.
Figure 16-163. SIMPLIFIED BLOCK DIAGRAM OF RAM1K18

The following table shows a simplified block diagram of the RAM1K18 memory block and gives the port descriptions.

Table 16-331. PORT RAM LIST FOR RAM1K18
Pin Name Pin Direction Type Description Polarity
A_ADDR[13:0] Input Dynamic Port A address —
A_BLK[2:0] Input Dynamic Port A block selects High
A_CLK Input Dynamic Port A clock Rising
A_DIN[17:0] Input Dynamic Port A write data —
A_DOUT[17:0] Output Dynamic Port A read data —
A_WEN[1:0] Input Dynamic Port A write enables (per byte) High
A_WIDTH[2:0] Input Static Port A width/depth mode select —
A_WMODE Input Static Port A feed-through write select High
A_ARST_N Input Dynamic Port A reset (must be tied to 1) Low
A_DOUT_LAT Input Static Port A pipeline register select Low
A_DOUT_ARST_N Input Dynamic Port A pipeline register asynchronous reset Low
A_DOUT_CLK Input Dynamic Port A pipeline register clock (must be tied to A_CLK or 1) Rising
A_DOUT_EN Input Dynamic Port A pipeline register enable High
A_DOUT_SRST_N Input Dynamic Port A pipeline register synchronous reset Low
B_ADDR[13:0] Input Dynamic Port B address —
B_BLK[2:0] Input Dynamic Port B block selects High
B_CLK Input Dynamic Port B clock Rising
B_DIN[17:0] Input Dynamic Port B write data —
B_DOUT[17:0] Output Dynamic Port B read data —
B_WEN[1:0] Input Dynamic Port B write enables (per byte) High
B_WIDTH[2:0] Input Static Port B width/depth mode select —
B_WMODE Input Static Port B Feed-through write select High
B_ARST_N Input Dynamic Port B reset (must be tied to 1) Low
B_DOUT_LAT Input Static Port B pipeline register select Low
B_DOUT_ARST_N Input Dynamic Port B pipeline register asynchronous reset Low
B_DOUT_CLK Input Dynamic Port B pipeline register clock (must be tied to B_CLK or 1) Rising
B_DOUT_EN Input Dynamic Port B pipeline register enable High
B_DOUT_SRST_N Input Dynamic Port B pipeline register synchronous reset Low
A_EN Input Static Port A power-down (must be tied to 1) Low
B_EN Input Static Port B power-down (must be tied to 1) Low
SII_LOCK Input Static Lock access to SII High
BUSY Output Dynamic Busy signal from SII High
Tip: Static inputs are defined at design time and need to be tied to 0 or 1.

Signal Descriptions for RAM1K18

A_WIDTH AND B_WIDTH

The following table lists the width/depth mode selections for each port. Two-port mode is in effect when the width of at least one port is 36, and A_WIDTH indicates the read width while B_WIDTH indicates the write width. Also, when the write width is 36, the read width must also be 36.

Table 16-332. WIDTH/DEPTH MODE SELECTION
Depth x Width A_WIDTH/B_WIDTH
16Kx1 000
8Kx2 001
4Kx4 010
2Kx8, 2Kx9 011
1Kx16, 1Kx18 100
512x32, 512x36

(Two-port)

 101

11x

A_WEN AND B_WEN

The following table lists the write/read control signals for each port. Two-port mode is in effect when the width of at least one port is 36, and read operation is always enabled. Also, when the write width is 36, both A_WEN and B_WEN must be static.

Table 16-333. WRITE/READ OPERATION SELECT
Depth x Width A_WEN/B_WEN Result
16Kx1, 8Kx2, 4Kx4, 2Kx8, 2Kx9, 1Kx16, 1Kx18 00 Perform a read operation
16Kx1, 8Kx2, 4Kx4, 2Kx8, 2Kx9 01 Perform a write operation
1Kx16 01 Write [7:0]
10 Write [16:9]
11 Write [16:9], [7:0]
1Kx18 01 Write [8:0]
10 Write [17:9]
11 Write [17:0]
512x32

(Two-port write)

 B_WEN[0] = 1 Write B_DIN[7:0]
B_WEN[1] = 1 Write B_DIN[16:9]
A_WEN[0] = 1 Write A_DIN[7:0]
A_WEN[1] = 1 Write A_DIN[16:9]
512x36

(Two-port write)

 B_WEN[0] = 1 Write B_DIN[8:0]
B_WEN[1] = 1 Write B_DIN[17:9]
A_WEN[0] = 1 Write A_DIN[8:0]
A_WEN[1] = 1 Write A_DIN[17:9]

A_ADDR AND B_ADDR

The following table address buses for the two ports. Fourteen bits are needed to address the 16K independent locations in x1 mode. In wider modes, fewer address bits are used. The required bits are MSB justified and unused LSB bits must be tied to 0. A_ADDR is synchronized by A_CLK while B_ADDR is synchronized to B_CLK. Two-port mode is in effect when the width of at least one port is 36, and A_ADDR provides the read address while B_ADDR provides the write address.

Table 16-334. ADDRESS BUS USED AND UNUSED BITS
Depth x Width A_ADDR/B_ADDR
Used Bits Unused Bits

(must be tied to 0)
16Kx1 [13:0] None
8Kx2 [13:1] [0]
4Kx4 [13:2] [1:0]
2Kx8, 2Kx9 [13:3] [2:0]
1Kx16, 1Kx18 [13:4] [3:0]
512x32,

512x36 (Two-port)

 [13:5] [4:0]

A_DIN AND B_DIN

The following table lists the data input buses for the two ports. The required bits are LSB justified and unused MSB bits must be tied to 0. Two-port mode is in effect when the width of at least one port is 36, and A_DIN provides the MSB of the write data while B_DIN provides the LSB of the write data.

Table 16-335. DATA INPUT BUSES USED AND UNUSED BITS
Depth x Width A_DIN/B_DIN
Used Bits Unused Bits

(must be tied to 0)
16Kx1 [0] [17:1]
8Kx2 [1:0] [17:2]
4Kx4 [3:0] [17:4]
2Kx8 [7:0] [17:8]
2Kx9 [8:0] [17:9]
1Kx16 [16:9] is [15:8]

[7:0] is [7:0]

 [17]

[8]
1Kx18 [17:0] None
512x32

(Two-port write)

 A_DIN[16:9] is [31:24]

A_DIN[7:0] is [23:16]

B_DIN[16:9] is [15:8]

B_DIN[7:0] is [7:0]

 A_DIN[17] A_DIN[8] B_DIN[17] B_DIN[8]
512x36

(Two-port write)

 A_DIN[17:0] is [35:18]

B_DIN[17:0] is [17:0]

 None

A_DOUT AND B_DOUT

The following table lists the data output buses for the two ports. The required bits are LSB justified. Two-port mode is in effect when the width of at least one port is 36, and A_DOUT provides the MSB of the read data while B_DOUT provides the LSB of the read data.

Table 16-336. DATA OUTPUT BUSES USED AND UNUSED BITS
Depth x Width A_DOUT/B_DOUT
Used Bits Unused Bits
16Kx1 [0] [17:1]
8Kx2 [1:0] [17:2]
4Kx4 [3:0] [17:4]
2Kx8 [7:0] [17:8]
2Kx9 [8:0] [17:9]
1Kx16 [16:9] is [15:8]

[7:0] is [7:0]

 [17]

[8]
1Kx18 [17:0] None
512x32

(Two-port read)

 A_DOUT[16:9] is [31:24]

A_DOUT[7:0] is [23:16]

B_DOUT[16:9] is [15:8]

B_DOUT[7:0] is [7:0]

 A_DOUT[17]

A_DOUT[8]

B_DOUT[17]

B_DOUT[8]
512x36

(Two-port read)

 A_DOUT[17:0] is [35:18]

B_DOUT[17:0] is [17:0]

 None

A_BLK AND B_BLK

The following table lists the block port select control signals for the two ports. A_BLK is synchronized by A_CLK while B_BLK is synchronized to B_CLK. Two-port mode is in effect when the width of at least one port is 36, and A_BLK controls the read operation while B_BLK controls the write operation.

Table 16-337. BLOCK PORT SELECT
Block Port Select Signal Value Result
A_BLK[2:0] 111 Perform read or write operation on Port A. In 36 width mode, perform a read operation from both ports A and B.
A_BLK[2:0] Any one bit is 0 No operation in memory from Port A. Port A read data will be forced to 0. In 36 width mode, the read data from both ports A and B will be forced to 0.
B_BLK[2:0] 111 Perform read or write operation on Port B. In 36 width mode, perform a write operation to both ports A and B.
B_BLK[2:0] Any one bit is 0 No operation in memory from Port B. Port B read data will be forced to 0, unless it is a 36 width mode and write operation to both ports A and B is gated.

A_WMODE AND B_WMODE

In true dual-port write mode, each port has a feed-through write option:

  • Logic 0 = Read data port holds the previous value.
  • Logic 1 = Feed-through, that is, write data appears on the corresponding read data port. This setting is invalid when the width of at least one port is 36 and the two-port mode is in effect.

A_CLK AND B_CLK

All signals in ports A and B are synchronous to the corresponding port clock. All address, data, block port select and write enable inputs must be setup before the rising edge of the clock. The read or write operation begins with the rising edge. Two-port mode is in effect when the width of at least one port is 36, and A_CLK provides the read clock while B_CLK provides the write clock:

  • A_DOUT_LAT and B_DOUT_LAT
  • A_DOUT_CLK and B_DOUT_CLK
  • A_DOUT_ARST_N and B_DOUT_ARST_N
  • A_DOUT_EN and B_DOUT_EN
  • A_DOUT_SRST_N and B_DOUT_SRST_N

The A_DOUT_LAT and B_DOUT_LAT signals select the pipeline registers for the respective port. Two-port mode is in effect when the width of at least one port is 36, and the A_DOUT register signals control the MSB of the read data while the B_DOUT register signals control the LSB of the read data.

The pipeline registers have rising edge clock inputs for each port, which must be tied to the respective port clock when used. When the pipeline registers are not being used, they are forced into latch mode and the clock signals must be tied to 1, which makes them transparent.

The following table lists the functionality of the control signals on the A_DOUT and B_DOUT pipeline registers.

Table 16-338. TRUTH TABLE FOR A_DOUT AND B_DOUT REGISTERS
_ARST_N _LAT _CLK _EN _SRST_N D Qn+1
0 X X X X X 0
1 0 Not rising X X X Qn
1 0 — 0 X X Qn
1 0 — 1 0 X 0
1 0 — 1 1 D D
1 1 0 X X X Qn
1 1 1 0 X X Qn
1 1 1 1 0 X 0
1 1 1 1 1 D D

A_EN AND B_EN

These are active-low, and power-down configuration bits for each port. They must be tied to 1.

A_ARST_N AND B_ARST_N

Always tie these signals to 1.

SII_LOCK

Control signal, when 1 locks the entire RAM1K18 memory from being accessed by the SII.

BUSY

This output indicates that the RAM1K18 memory is being accessed by the SII.

RAM64X18

The RAM64x18 block contains 1,152 memory bits and is a three-port memory providing one write port and two read ports. Write operations to the RAM64x18 memory are synchronous. Read operations can be asynchronous or synchronous for either setting up the address and/or reading out the data. Enabling synchronous operation at the read address port improves setup timing for the read address and its enable signals. Enabling synchronous operation at the read data port improves clock-to-out delay. Each data port on the RAM64x18 memory can be independently configured in any combination as shown in the following list:

  • 64x18, 64x16
  • 128x9, 128x8
  • 256x4
  • 512x2
  • 1Kx1

The main features of the RAM64x18 memory block are as follows:

  • There are two independent read data ports A and B, and one write data port C.
  • The write operation is always synchronous. The write address, write data, C block port select and write enable inputs are registered.
  • For both read data ports, setting up the address can be synchronous or asynchronous.
  • The two read data ports have address registers with a separate enable, synchronous-reset, and asynchronous-reset for synchronous mode operation, which can also be configured to be transparent latches for asynchronous mode operation.
  • The two read data ports have output registers with a separate enable, synchronous-reset, and asynchronous-reset for pipeline mode operation, which can also be configured to be transparent latches for asynchronous mode operation. Therefore, there are four read operation modes for ports A and B:
    • Synchronous read address without pipeline registers (sync-async).
    • Synchronous read address with pipeline registers (sync-sync).
    • Asynchronous read address without pipeline registers (async-async).
    • Asynchronous read address with pipeline registers (async-sync).
  • Each data port on the RAM64x18 memory can be independently configured in any of the following combinations: 64x18, 64x16, 128x9, 128x8, 256x4, 512x2, and 1Kx1.
  • The widths of each port can be different, but they need to be multiples of one another.
  • There is an independent clock for each port. The memory is triggered at the rising edge of the clock.
  • Read from both ports A and B at the same location is allowed.
  • Read and write on the same location at the same time results in unknown data to be read. There is no collision prevention or detection. However, correct data are expected to be written into the memory.
The following figure shows a simplified block diagram of the RAM64x18 memory block and the following table gives the port descriptions. The simplified block diagram illustrates the three independent read/write ports and the pipeline registers on the read port.
Figure 16-164. SIMPLIFIED BLOCK DIAGRAM OF RAM64X18
Table 16-339. PORT LIST FOR RAM64X18
Pin Name Pin Direction Type Description Polarity
A_ADDR[9:0] Input Dynamic Port A address —
A_BLK[1:0] Input Dynamic Port A block selects High
A_WIDTH[2:0] Input Static Port A width/depth mode selection —
A_DOUT[17:0] Output Dynamic Port A read data —
A_DOUT_ARST_N Input Dynamic Port A pipeline register asynchronous reset Low
A_DOUT_CLK Input Dynamic Port A pipeline register clock Rising
A_DOUT_EN Input Dynamic Port A pipeline register enable High
A_DOUT_LAT Input Static Port A pipeline register select Low
A_DOUT_SRST_N Input Dynamic Port A pipeline register synchronous reset Low
A_ADDR_CLK Input Dynamic Port A address register clock Rising
A_ADDR_EN Input Dynamic Port A address register enable High
A_ADDR_LAT Input Static Port A address register select Low
A_ADDR_SRST_N Input Dynamic Port A address register synchronous reset Low
A_ADDR_ARST_N Input Dynamic Port A address register asynchronous reset Low
B_ADDR[9:0] Input Dynamic Port B address —
B_BLK[1:0] Input Dynamic Port B block selects High
B_WIDTH[2:0] Input Static Port B width/depth mode selection —
B_DOUT[17:0] Output Dynamic Port B read data —
B_DOUT_ARST_N Input Dynamic Port B pipeline register asynchronous reset Low
B_DOUT_CLK Input Dynamic Port B pipeline register clock Rising
B_DOUT_EN Input Dynamic Port B pipeline register enable High
B_DOUT_LAT Input Static Port B pipeline register select Low
B_DOUT_SRST_N Input Dynamic Port B pipeline register synchronous reset Low
B_ADDR_CLK Input Dynamic Port B address register clock Rising
B_ADDR_EN Input Dynamic Port B address register enable High
B_ADDR_LAT Input Static Port B address register select Low
B_ADDR_SRST_N Input Dynamic Port B address register synchronous reset Low
B_ADDR_ARST_N Input Dynamic Port B address register asynchronous reset Low
C_ADDR[9:0] Input Dynamic Port C address —
C_CLK Input Dynamic Port C clock Rising
C_DIN[17:0] Input Dynamic Port C write data —
C_WEN Input Dynamic Port C write enable High
C_BLK[1:0] Input Dynamic Port C block selects High
C_WIDTH[2:0] Input Static Port C width/depth mode selection —
A_EN Input Static Port A power-down (must be tied to 1) Low
B_EN Input Static Port B power-down (must be tied to 1) Low
C_EN Input Static Port C power-down (must be tied to 1) Low
SII_LOCK Input Static Lock access to SII High
BUSY Output Dynamic Busy signal from SII High
Tip: Static inputs are defined at design time and need to be tied to 0 or 1.

Signal Descriptions for RAM64x18

A_WIDTH, B_WIDTH AND C_WIDTH

The following table lists the width/depth mode selections for each port.

Table 16-340. WIDTH/DEPTH MODE SELECTION
Depth x Width A_WIDTH/B_WIDTH/C_WIDTH
1Kx1 000
512x2 001
256x4 010
128x8, 128x9 011
64x16, 64x18 1xx

C_WEN

This is the write enable signal for port C.

A_ADDR, B_ADDR AND C_ADDR

The following table lists the address buses for each port. 10 bits are required to address 1K independent locations in x1 mode. In wider modes, fewer address bits are used. The required bits are MSB justified and unused LSB bits must be tied to 0.

Table 16-341. ADDRESS BUSES USED AND UNUSED BITS
Depth x Width A_ADDR/B_ADDR/C_ADDR
Used Bits Unused Bits

(must be tied to zero)
1Kx1 [9:0] None
512x2 [9:1] [0]
256x4 [9:2] [1:0]
128x8, 128x9 [9:3] [2:0]
64x16, 64x18 [9:4] [3:0]

C_DIN

The following table lists the write data input for port C. The required bits are LSB justified and unused MSB bits must be tied to 0.

Table 16-342. DATA INPUT BUS USED AND UNUSED BITS
Depth x Width C_DIN
Used Bits Unused Bits

(must be tied to 0)
1Kx1 [0] [17:1]
512x2 [1:0] [17:2]
256x4 [3:0] [17:4]
128x8 [7:0] [17:8]
128x9 [8:0] [17:9]
64x16 [16:9]

[7:0]

 [17]

[8]
64x18 [17:0] None

A_DOUT AND B_DOUT

The following table lists the read data output buses for ports A and B. The required bits are LSB justified.

Table 16-343. DATA OUTPUT USED AND UNUSED BITS
Depth x Width A_DOUT/B_DOUT
Used Bits Unused Bits
1Kx1 [0] [17:1]
512x2 [1:0] [17:2]
256x4 [3:0] [17:4]
128x8 [7:0] [17:8]
128x9 [8:0] [17:9]
64x16 [16:9] [7:0] [17] [8]
64x18 [17:0] None

A_BLK, B_BLK AND C_BLK

The following table lists the block port select control signals for the ports.

Table 16-344. BLOCK PORT SELECT
Block Port Select Signal Value Result
A_BLK[1:0] Any one bit is 0 Port A is not selected and its read data are forced to zero.
11 Perform read operation from port A.
B_BLK[1:0] Any one bit is 0 Port B is not selected and its read data are forced to zero.
11 Perform read operation from port B.
C_BLK[1:0] Any one bit is 0 Port C is not selected.
11 Perform write operation to port C.

C_CLK

All signals on port C are synchronous to this clock signal. All write address, write data, C block port select and write enable inputs must be setup before the rising edge of the clock. The write operation begins with the rising edge:

  • A_DOUT_LAT, A_ADDR_LAT, B_DOUT_LAT, and B_ADDR_LAT
  • A_DOUT_CLK, A_ADDR_CLK, B_DOUT_CLK, and B_ADDR_CLK
  • A_DOUT_ARST_N, A_ADDR_ARST_N, B_DOUT_ARST_N, and B_ADDR_ARST_N
  • A_DOUT_EN, A_ADDR_EN, B_DOUT_EN, and B_ADDR_EN
  • A_DOUT_SRST_N, A_ADDR_SRST_N, B_DOUT_SRST_N, and B_ADDR_SRST_N
  • The _LAT signals select the registers for the respective port.

The address and pipeline registers have rising edge clock inputs for ports A and B. When both the address and pipeline registers for a port are in use, their clock signals must be tied together. When the registers are not being used, they are forced into latch mode and the clock signals must be tied to 1, which makes them transparent.

The following table lists the functionality of the control signals on the A_ADDR, B_ADDR, A_DOUT, and B_DOUT registers.

Table 16-345. TRUTH TABLE FOR A_ADDR, B_ADDR, A_DOUT, AND B_DOUT REGISTERS
_ARST_N _LAT _CLK _EN _SRST_N D Qn+1
0 X X X X X 0
1 0 Not rising X X X Qn
1 0 — 0 X X Qn
1 0 — 1 0 X 0
1 0 — 1 1 D D
1 1 0 X X X Qn
1 1 1 0 X X Qn
1 1 1 1 0 X 0
1 1 1 1 1 D D

A_EN, B_EN AND C_EN

Active-Low, power-down configuration bits for each port. They must be tied to 1.

SII_LOCK

Control signal, when 1 locks the entire RAM64X18 memory from being accessed by the SII.

BUSY

Output indicates that the RAM64X18 memory is being accessed by the SII.