The DDR_OE_UNIT macro is an output DDR cell that is only available for
post-layout simulations. Every DDR_OUT instance is replaced by DDR_OE_UNIT during compile.
The DDR_OE_UNIT macro consists of a DDR_OUT macro with inverted data inputs and SDR
control.Figure 16-116. DDR_OE_UNIT
Table 16-255. DDR_OE_UNIT I/O
Input
Output
Name
Function
DRn
Data input (Rising Edge)
Q
DFn
Data input (Falling Edge)
CLK
Clock input
EN
Active-High CLK enable
ALn
Asynchronous load. This active-low signal
either sets the register or clears the register depending on the value of
ADn.
ADn
Static asynchronous load data. When ALn is active, Q goes to the complement of ADn.
SLn
Synchronous load. This active-Low signal
either sets the register or clears the register depending on the value of SD,
at the rising edge of CLK.
SD
Static synchronous load data. When SLn is
active (low), Q goes to the value of SD at the rising edge of CLK.
SDR
Controls whether the cell operates in DDR (SDR = 0) or SDR (SDR = 1) modes.
The DDR_OUT macro is an output DDR cell and is available for pre-layout
simulation. It consists of two SLE macros. The output Q must be connected to an I/O.Figure 16-117. DDR_OUT
Table 16-257. DDR_OUT I/O
Input
Output
Name
Function
DR
Data input (Rising Edge)
Q
DF
Data input (Falling Edge)
CLK
Clock input
EN
Active-High CLK enable
ALn
Asynchronous load. This active-low signal either sets the
register or clears the register depending on the value of ADn.
The UJTAG macro is a special purpose macro. It allows access to the user JTAG circuitry on board the chip.
You must instantiate a UJTAG macro in your design if you plan to make use of the user JTAG feature. The TMS, TDI, TCK, TRSTB, and TDO pins of the macro must be connected to top level ports of the design.Figure 16-132. UJTAG
Table 16-287. Ports and Descriptions
Port
Direction
Polarity
Description
UIREG[7:0]
Output
—
This 8-bit bus carries the contents of the JTAG instruction register of each device. Instruction values 16 to 127 are not reserved and can be employed as user-defined instructions.
URSTB
Output
Low
URSTB is an Active-Low signal and is asserted when the TAP controller is in Test-Logic-Reset mode. URSTB is asserted at power-up, and a Power-on Reset signal resets the TAP controller state.
UTDI
Output
—
This port is directly connected to the TAP's TDI signal.
UTDO
Input
—
This port is the user TDO output. Inputs to the UTDO port are sent to the TAP TDO output MUX when the IR addess is in user range.
UDRSH
Output
High
Active-High signal enabled in the Shift_DR TAP state.
UDRCAP
Output
High
Active-High signal enabled in the Capture_DR_TAP state.
UDRCK
Output
—
This port is directly connected to the TAP's TCK signal.
Note: UDRCK must be connected to a global macro such as CLKINT. If this is not done, Synthesis/Compile will add it to the netlist to legalize it.
UDRUPD
Output
High
Active-High signal enabled in the Update_DR_TAP state.
TCK
Input
—
Test Clock. Serial input for JTAG boundary scan, ISP, and
UJTAG. The TCK pin does not have an internal pull-up/pull-down resistor.
Connect TCK to GND or +3.3V through a resistor (500-1 KΩ) placed closed
to the FPGA pin to prevent totem-pole current on the input buffer and
TMS from entering into an undesired state.
If JTAG is
not used, connect it to GND.
TDI
Input
—
Test Data In. Serial input for JTAG boundary scan. There is an internal weak pull-up resistor on the TDI pin.
TDO
Output
—
Test Data Out. Serial output for JTAG boundary scan. The TDO pin does not have an internal pull-up/pull-down resistor.
TMS
Input
—
Test mode select. The TMS pin controls the use of the IEEE®1532 boundary scan pins (TCK, TDI, TDO, and TRST).
There is an internal weak pull-up resistor on the TMS pin.
TRSTB
Input
Low
Test reset. The TRSTB pin is an active-low input. It
synchronously initializes (or resets) the boundary scan circuitry. There
is an internal weak pull-up resistor on the TRSTB pin.
To hold the JTAG in reset mode and prevent it from
entering into undesired states in critical applications, connect
TRSTB to GND through a 1 KΩ resistor (placed close to the FPGA
pin).
