13.1 About SmartTime

Static Timing Analysis (STA) offers an efficient technique for identifying timing violations in your design and ensuring that it meets all your timing requirements. You can communicate timing requirements and timing exceptions to the system by setting timing constraints. Then a static timing analysis tool checks and reports setup, and holds violations and violations on specific path requirements.

STA is particularly well suited for traditional synchronous designs. The main advantage of STA is that unlike dynamic simulation, it does not require input vectors. It covers all possible paths in the design and does all the above with relatively low run-time requirements.

A major disadvantage of STA is that the STA tools do not automatically detect false paths in their algorithms as it reports all possible paths, including false paths, in the design. False paths are timing paths in the design that do not propagate a signal. To get a true and useful timing analysis, identify any false paths as false path constraints to the STA tool and exclude them from timing considerations.

The SmartTime user interface provides efficient, user-friendly ways to define these critical false paths.

SmartTime supports a range of timing constraints to provide useful analysis and efficient timing-driven layout.

SmartTime provides a selection of analysis types that allow you to:

• Find the minimum clock period/highest frequency that does not result in a timing violations
• Identify paths with timing violations
• Analyze delays of paths that have no timing constraints
• Perform inter-clock domain timing verification
• Perform maximum and minimum delay analysis for setup and hold checks

To improve the accuracy of the results, SmartTime evaluates clock skew during timing analysis by computing individual clock insertion delays for each register.

SmartTime checks the timing requirements for violations while evaluating timing exceptions such as multicycle or false paths.

Libero SoC Place and Route uses SmartTime STA during timing-driven place-and-route operations run in the background. As a result, your analysis and place and route constraints are always consistent.

SmartTime provides robust reporting capabilities that allow you to generate the following report files:

• Timing Report for Max and Min Delay Analysis
• Timing Violations Report for Max and Min Delay Analysis
• Bottleneck Report
• Constraints Coverage Report
• Combinational Loop Report

From SmartTime, you can select a design object and cross-probe the same design object in Chip Planner.

Design objects that can be cross-probed from SmartTime to Chip Planner include:

• Ports
• Macros
• Timing paths

From SmartTime, you can cross-probe into the Constraints Editor. The Constraints Editor must be running for cross-probing to work.

For more information, see section 13.9.9.3 Cross-Probing from SmartTime to Chip Planner.