3.4.1 SAMA5D27/BGA289/LPDDR1-SDRAM Devices

Figure 3-36. MPUx-DRAMx-v2 LPDDR Device

This set features a SAMA5D27/BGA289 MPU and one 512-Mbit LPDDR-SDRAM device (Part No.: W949D2DBJX5I).

Figure 3-37. SAMA5D27/BGA289/LPDDR1-SDRAM Layer 1 (TOP)

The top layer of this test board shown in the above figure contains part of the data and address traces of this set. The trace width for single-ended signals on the top layer is 5 mils and it easily achieves a near 50Ω trace impedance, according to the specifications. The trace clearance is 11 mils, above the minimum.

The differential CK/CKn signal traces are 4 mils wide and clearance between the differential traces of 6 mils, achieving an impedance very close to 100Ω.

When calculating the single-ended or differential trace impedance on top or bottom layers, the effect of the solder mask must be considered.

In case of a dense or complicated board design, if the signals within the same byte lane cannot be routed in the same layer, it is possible to have some signals routed on other layers, thus violating the same layer byte lane rule.

Figure 3-38. SAMA5D27/BGA289/LPDDR1-SDRAM Layer 2

Layer 2 of the test board serves as ground plane as well as impedance-matching reference for the neighboring signal layers (layers 1 and 3). The region shown in the above figure provides the return path for the SDRAM device. It covers a large surface and does not feature any splits over high-speed signals thus ensuring good signal integrity.

Figure 3-39. SAMA5D27/BGA289/LPDDR1-SDRAM Layer 4

The figure above shows layer 4 of the test board, centered on the LPDDR1-SDRAM set. While most of the traces have clearances above or at the same value as the minimum, in small regions it is acceptable to have a reduced clearance due to physical constraints.

It is important to have all signals within the same byte lane tightly length-matched. In this design, the traces within any byte lane have a length mismatch of maximum 6 mils.