9.12.3 CHEHIT – Prefetch Module Hit Statistics Register
| Name: | CHEHIT |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CHEHIT[31:24] | |||||||||
| Access | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHEHIT[23:16] | |||||||||
| Access | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHEHIT[15:8] | |||||||||
| Access | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHEHIT[7:0] | |||||||||
| Access | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – CHEHIT[31:0] Instruction Cache Hit Count bits
1, CHEHIT increments once per iCache or Predictive Prefetch
Buffer (PFB) hit. Note: CHEHIT is
Reset on
0 to 1 transition of
CHECON.CHEPERF.