9.12.2 CHESTAT - Prefetch Module Status Register

Name: CHESTAT
Offset: 0x10
Reset: 0x00000000
Property: -

Bit 3130292827262524 
     PFMDEDPFMSEC   
Access HS, R/CHS, R/W 
Reset 00 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 PFMSECCNT[7:0] 
Access HS, HC, R/WHS, HC, R/WHS, HC, R/WHS, HC, R/WHS, HC, R/WHS, HC, R/WHS, HC, R/WHS, HC, R/W 
Reset 00000000 

Bit 27 – PFMDED Flash Double-bit Error Detected (DED) Status bit

This bit is set in hardware and can only be cleared (i.e., set to ‘0’) in software.
ValueDescription
1 A DED error has occurred
0

A DED error has not occurred

Bit 26 – PFMSEC Flash Single-bit Error Corrected (SEC) Status bit

Note: The error event is reported to the CPU via using the PCACHE interrupt event (See Nested Vector

Interrupt Controller (NVIC) from Related Links).

ValueDescription
1

A SEC error occurred when PFMSECCNT[7:0] was equal to zero
0

A SEC error has not occurred

Bits 7:0 – PFMSECCNT[7:0] Flash SEC Count bits

Decrements by 1 its count value each time an SEC error occurs. Holds at zero. When an SEC error occurs when PFMSECCNT[7:0] is zero, the PFMSEC status bit is set. If PFMSECEN is also set, a Prefetch module interrupt event is generated.