9.12.4 CHEMIS – Prefetch Module Miss Statistics Register
| Name: | CHEMIS |
| Offset: | 0x30 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CHEMIS[31:24] | |||||||||
| Access | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHEMIS[23:16] | |||||||||
| Access | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHEMIS[15:8] | |||||||||
| Access | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHEMIS[7:0] | |||||||||
| Access | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | R/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – CHEMIS[31:0] Instruction Cache Miss Count bits
1, CHEMIS increments once per iCache or Predictive Prefetch
Buffer (PFB) miss. Note: CHEMIS is
Reset on
0 to 1 transition of
CHECON.CHEPERF.