13.2 Features

The Clock and Reset Unit has the following features:

  • Supports the following as system clock sources:
    • 16 MHz Primary Crystal Oscillator (POSC)
    • 8 MHz Fast RC Oscillator (FRC)
    • 32 kHz Low Power RC Oscillator (LPRC)
    • 32.768 kHz Secondary Crystal Oscillator (SOSC)
    • 96 MHz System PLL (RFPLL)
  • Provides control registers for all PLLs
  • Provides for glitch-free clock switching between various clock sources
  • Post dividers on processor clock generator to slow down system clock for power save
  • A fail safe clock monitor that detects clock failure and provides automatic switching to the FRC
  • Provides control registers for user interface of clocks and resets
  • Provides configuration bits for oscillator selection and calibration of on-chip oscillators
  • Provides control registers to generate a reference clock output
  • Provide resets for the system
  • Provides NMI interrupts for the system
  • Multiple PB clock dividers
  • One system clock, SYS_CLK, from which almost all clocks used throughout the system are derived
  • Three peripheral clocks, created by independent integer dividers of the SYS_CLK:
    • PB1_CLK: PB-PIC and PB-Bridge-A bus
    • PB2_CLK: PB-Bridge-B and PB-Bridge-C
    • PB3_CLK: DS/XDS bus clock
  • Six reference output clocks (REFO1 – REFO6) with the following clock sources:
    • System clock (SYS_CLK)
    • PB1 bus clock (PB1_CLK)
    • 16 MHz Primary Crystal Oscillator (POSC)
    • 8 MHz Fast RC Oscillator (FRC)
    • 32 kHz Low Power RC Oscillator (LPRC)
    • 32.768 kHz Secondary Crystal Oscillator (SOSC)
    • 96 MHz System PLL (RFPLL)
    • 64 MHz System PLL (RFPLL PGM MHz)
    • REFI pin
    • Sleep control, supporting Req/Ack signaling with the bus matrix to determine that no transactions are in flight when initiating sleep
  • JTAG TCK clock control