32.11.1 Chip Select Wait States

The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one.

During Chip Select Wait state, all control lines are turned inactive: NBS0 to NBS1, NWR0 to NWR1, NCS[0..2], NRD lines are all set to 1.

The following figure illustrates a Chip Select Wait state between accesses on Chip Select 0 and Chip Select 2.

Figure 32-14. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2