32.11.2 Early Read Wait State

In some cases, the SMC inserts a Wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This Wait state is not generated in addition to a Chip Select Wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select).

An Early Read Wait state is automatically inserted if at least one of the following conditions is valid:

The write controlling signal has no hold time and the read controlling signal has no setup time (Figure 32-15).
In NCS Write Controlled mode (WRITE_MODE = 0), there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 32-16). The write operation must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.
In NWE Controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 32-17.

Figure 32-15. Early Read Wait State: Write with No Hold Followed by Read with No Setup

Figure 32-16. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup

Figure 32-17. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle