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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Product Pages
SAM9X70 SAM9X72 SAM9X75
  1. Home
  2. 32 Static Memory Controller (SMC)
  3. 32.10 Standard Read and Write Protocols
  4. 32.10.6 Reset Values of Timing Parameters
  • Introduction
  • Features
  • 1 Configuration Summary
  • 2 Block Diagram
  • 3 Signal Description
  • 4 Microchip Recommended Power Management Solutions
  • 5 Safety and Security Features
  • 6 Package and Pinout
  • 7 Peripherals
  • 8 Arm926EJ-S Processor
  • 9 Debug and Test
  • 10 Bus Matrix (MATRIX)
  • 11 DMA Controller (XDMAC)
  • 12 Boot Strategies
  • 13 SYSTEM CONTROLLER SUBSYSTEM
  • 14 System Controller Write Protection (SYSCWP)
  • 15 Advanced Interrupt Controller (AIC)
  • 16 Boot Sequence Controller (BSC)
  • 17 General Purpose Backup Registers (GPBR)
  • 18 Watchdog Timer (WDT)
  • 19 Reset Controller (RSTC)
  • 20 Real-Time Timer (RTT)
  • 21 Real-time Clock (RTC)
  • 22 Shutdown Controller (SHDWC)
  • 23 Periodic Interval Timer (PIT)
  • 24 64-bit Periodic Interval Timer (PIT64B)
  • 25 Debug Unit (DBGU)
  • 26 Special Function Registers (SFR)
  • 27 Slow Clock Controller (SCKC)
  • 28 Clock Generator
  • 29 Power Management Controller (PMC)
  • 30 Parallel Input/Output Controller (PIO)
  • 31 MEMORIES
  • 32 Static Memory Controller (SMC)
    • 32.1 Description
    • 32.2 Embedded Characteristics
    • 32.3 I/O Lines Description
    • 32.4 Interrupt Source
    • 32.5 Multiplexed Signals
    • 32.6 Application Example
    • 32.7 Product Dependencies
    • 32.8 External Memory Mapping
    • 32.9 Connection to External Devices
    • 32.10 Standard Read and Write Protocols
      • 32.10.1 Read Waveforms
      • 32.10.2 Read Mode
      • 32.10.3 Write Waveforms
      • 32.10.4 Write Mode
      • 32.10.5 Coding Timing Parameters
      • 32.10.6 Reset Values of Timing Parameters
      • 32.10.7 Usage Restriction
    • 32.11 Automatic Wait States
    • 32.12 Data Float Wait States
    • 32.13 External Wait
    • 32.14 Slow Clock Mode
    • 32.15 Asynchronous Page Mode
    • 32.16 Register Write Protection
    • 32.17 Security and Safety Analysis and Reports
    • 32.18 Scrambling/Unscrambling Function
    • 32.19 Clearing Scrambling Keys on a Tamper Event
    • 32.20 Register Summary
  • 33 Programmable Multibit Error Correction Code Controller (PMECC)
  • 34 Programmable Multibit ECC Error Location Controller (PMERRLOC)
  • 35 DDR-SDRAM Controller (MPDDRC)
  • 36 OTP Memory Controller (OTPC)
  • 37 IMAGE SUBSYSTEM
  • 38 LCD Controller (LCDC)
  • 39 Low Voltage Differential Signaling Controller (LVDSC)
  • 40 2D Graphics Engine (GFX2D)
  • 41 Display Serial Interface (DSI)
  • 42 Camera Serial Interface (CSI)
  • 43 CSI-2 Demultiplexer Controller (CSI2DC)
  • 44 Image Sensor Controller (ISC)
  • 45 AUDIO SUBSYSTEM
  • 46 Audio Class D Amplifier (CLASSD)
  • 47 Inter-IC Sound Multi-Channel Controller (I2SMCC)
  • 48 Synchronous Serial Controller (SSC)
  • 49 CRYPTOGRAPHY SUBSYSTEM
  • 50 Advanced Encryption Standard (AES)
  • 51 Secure Hash Algorithm (SHA)
  • 52 Triple Data Encryption Standard (TDES)
  • 53 True Random Number Generator (TRNG)
  • 54 Physical Unclonable Functions (PUF)
  • 55 CONNECTIVITY SUBSYSTEM
  • 56 Ethernet MAC (GMAC)
  • 57 Flexible Serial Communication Controller (FLEXCOM)
  • 58 Quad Serial Peripheral Interface (QSPI)
  • 59 Secure Digital MultiMedia Card Controller (SDMMC)
  • 60 Controller Area Network (MCAN)
  • 61 Timer Counter (TC)
  • 62 Pulse Width Modulation Controller (PWM)
  • 63 USB SUBSYSTEM
  • 64 USB Device High Speed Port (UDPHS)
  • 65 USB Host High Speed Port (UHPHS)
  • 66 Analog-to-Digital Controller (ADC)
  • 67 Electrical Characteristics
  • 68 Mechanical Characteristics
  • 69 Marking
  • 70 Ordering Information
  • 71 Revision History
  • Microchip Information

32.10.6 Reset Values of Timing Parameters

For the default values of timing parameters at reset, see SMC_SETUPx, SMC_PULSEx and SMC_CYCLEx.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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