58.6.8.11 Octal DDR Mode

Some memories support Octal DDR communication. To enable Octal DDR mode, configure QSPI_IFR.WIDTH to either ‘7’, ‘8’ or ‘9’ and QSPI_IFR.DDREN to ‘1’. Configure the other parameters in QSPI_IFR to the targeted memory.

In this mode, QSPI_TDR.TD and QSPI_RDR.RD use the full 16-bit width.

For memories using 8-bit registers:
  • SMRM = 0

    The memory register can be read/written by performing a byte access in the QSPI memory space. In the case of a read, only the first byte read is considered. In the case of a write, check if the memory supports receiving the register value only on the first byte. If not, a halfword access must be performed (refer to the memory data sheet to build the halfword).

  • SMRM = 1

    In Octal DDR mode, QSPI_TDR.TD and QSPI_RDR.RD use the full 16-bit width. Therefore, it is mandatory to write/read a halfword in this configuration.