58.6.8.12 HyperFlash Mode

The QSPI supports HyperFlash memories. To enable HyperFlash mode, QSPI_IFR.PROTTYP must be written to ‘3’.

HyperFlash memories use Octal DDR communication. The recommendations given in Octal DDR Mode must be followed.

In HyperFlash memories, the address field is merged with the instruction field so QSPI_IFR.ADDREN must be set to ‘0’ in this mode even if the address is used. There is no use of instruction code, therefore QSPI_WICR and QSPI_RICR are not used in this mode.

Once HyperFlash mode is enabled, the procedure to access the memory is the same as for classic QSPI memories. See Instruction Frame Transmission.

For the HyperFlash Write Buffer procedure, QSPI_IFR.HFWBEN must be set. When this bit is set, a new command will be issued for each halfword written. In this mode, halfword size accesses are mandatory. See Figure 58-17 and Figure 58-18.

Note: In HyperFlash mode some bits of the HyperFlash command are automatically and seamlessly set. Thus the “Burst Type” bit of the HyperFlash command (bit 45) will always be set to 1 (linear Burst) using HyperFlash mode.