10.2.2 Import the false_path Verilog File and Add Constraints

For this tutorial, you will import the false_path.v Verilog source file into your design, and then run Libero SoC.
To import the Verilog source file:
  1. From the File menu, choose Import > HDL Source Files.
  2. Browse to the location of the false_path.v you saved and select it. Click Open to import the file.
  3. Verify that the file appears in Design Hierarchy.
  4. In the Design Flow window, double-click Synthesize to run synthesis.
    A green check mark appears when the Synthesis step completes successfully.
  5. Expand Edit Constraints.
  6. Right-click Timing Constraints and choose Open Interactively.
  7. Double-click Manage Constraints.
  8. Select the Timing tab.
  9. Expand the Edit with Constraint Editor sub-menu, and select Edit Place and Route Constraints.
    The Constraints Editor appears.
  10. Double-click Requirements: Clock.
    The Create Clock Constraint dialog box appears.
  11. Double click the Browse button for Clock Source, select CLK, and assign it a name (for example, clk).
  12. Set the frequency to 100 MHz.
    Figure 10-24. Clock Constraint of 100 MHz
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  13. Click OK to return to the Constraints Editor and observe that the clock information has been filled in, as shown in the following figure.
    Figure 10-25. Clock Constraint of 100 MHz in false_path design
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  14. Save your changes (File > Save) and close the Constraints Editor (File > Close).
  15. In the Constraint Manager, check the check boxes under Place and Route and Timing Verification to associate the constraint file to both tools. The constraint file is used for both Place and Route and Timing verification.