45.5.2 IEEE 1588 Time Stamp Unit

The IEEE 1588 time stamp unit (TSU) is implemented as a 102-bit timer.

• The 48 upper bits [93:46] of the timer count seconds and are accessible in the ETH 1588 Timer Seconds High Register” (TSH) and ETH 1588 Timer Seconds Low Register (TSL)
• The 30 lower bits [45:16] of the timer count nanoseconds and are accessible in the ETH 1588 Timer Nanoseconds Register (TN)
• TISUBN register specifies the increment value in sub nanoseconds for every clock

The 46 lower bits roll over when they have counted to 1s. The timer increments by a programmable period (to approximately 15.2 femtosecond resolution) with each CLK_ETH_TSU period and can also be adjusted in 1ns resolution (incremented or decremented) through APB register accesses.