7.2.6 System Pin List

Table 7-6. System Pin Description
Pin No.	Pin Name	Power Rail	I/O Type	Description	Active Level
29	MIPI_CK_N	VDD_2V5	PHY	MIPI DPHY negative differential output clock lane	–
30	MIPI_CK_P	VDD_2V5	PHY	MIPI DPHY positive differential output clock lane	–
25	MIPI_D0_N	VDD_2V5	PHY	MIPI DPHY negative differential output data lane 0	–
26	MIPI_D0_P	VDD_2V5	PHY	MIPI DPHY positive differential output data lane 0	–
27	MIPI_D1_N	VDD_2V5	PHY	MIPI DPHY negative differential output data lane 1	–
28	MIPI_D1_P	VDD_2V5	PHY	MIPI DPHY positive differential output data lane 1	–
31	MIPI_D2_N	VDD_2V5	PHY	MIPI DPHY negative differential output data lane 2	–
32	MIPI_D2_P	VDD_2V5	PHY	MIPI DPHY positive differential output data lane 2	–
33	MIPI_D3_N	VDD_2V5	PHY	MIPI DPHY negative differential output data lane 3	–
34	MIPI_D3_P	VDD_2V5	PHY	MIPI DPHY positive differential output data lane 3	–
185	USBA_P	VDD_3V3	USBPHY	USB host port A high-speed data +	–
184	USBA_N	VDD_3V3	USBPHY	USB host port A high-speed data -	–
187	USBB_P	VDD_3V3	USBPHY	USB host port B high-speed data +	–
186	USBB_N	VDD_3V3	USBPHY	USB host port B high-speed data -	–
189	USBC_P	VDD_3V3	USBPHY	USB host port C high-speed data +	–
188	USBC_N	VDD_3V3	USBPHY	USB host port C high-speed data -	–
130	PIOBU0	VBAT	Backup I/O	Tamper input/output 0 / Wake-up 2 input	–
132	PIOBU1	VBAT	Backup I/O	Tamper input/output 1 / Wake-up 3 input	–
131	PIOBU2	VBAT	Backup I/O	Tamper input/output 2 / Wake-up 4 input	–
133	PIOBU3	VBAT	Backup I/O	Tamper input/output 3 / Wake-up 5 input	–
134	JTAGSEL	VBAT	Backup I/O	JTAG selection	–
129	WKUP	VBAT	Backup I/O	Wake-up input. 100 kΩ internal pull-up.	–
135	SHDN	VBAT	Backup I/O	Shutdown control	Low
173	NRST	VDD_3V3	Input/Output	External nReset input/output. 10 kΩ internal pull-up.	Low
174	NRST_OUT	VDD_3V3	Output I/O	Microprocessor reset output	Low
147	AUDIOCLK	VDD_3V3	Output	Audio clock output	–
162	RSV0	–	–	Reserved. Connect to GND.	–
163	RSV1	–	–	Reserved. Connect to GND.	–
97	NAND_WP	VDD_3V3	Input	NAND Flash write protect. 100 kΩ internal pull-up.	Low
49	NAND_CS_IN	VDD_3V3	Input	NAND Flash chip select input. 100 kΩ internal pull-up.	Low
77	QSPI0_CS_IN	VDD_3V3	Input	NOR Flash chip select input. 10 kΩ internal pull-up.	Low
109	TXRXA_P	VDD_1V1_ETH	Input/Output	Physical receive or transmit signal (+ differential)	–
110	TXRXA_M	VDD_1V1_ETH	Input/Output	Physical receive or transmit signal (– differential)	–
112	TXRXB_P	VDD_1V1_ETH	Input/Output	Physical receive or transmit signal (+ differential)	–
113	TXRXB_M	VDD_1V1_ETH	Input/Output	Physical receive or transmit signal (– differential)	–
115	TXRXC_P	VDD_1V1_ETH	Input/Output	Physical receive or transmit signal (+ differential)	–
116	TXRXC_M	VDD_1V1_ETH	Input/Output	Physical receive or transmit signal (– differential)	–
118	TXRXD_P	VDD_1V1_ETH	Input/Output	Physical receive or transmit signal (+ differential)	–
119	TXRXD_M	VDD_1V1_ETH	Input/Output	Physical receive or transmit signal (– differential)	–
104	GMAC_LED5_ALLPHYAD	VDD_3V3	Input/Output	Programmable LED5 output/PHY Address Strap pin	–
103	GMAC_LED4_MAGJACK	VDD_3V3	Input/Output	Programmable LED4 output/MagJack register settings. 10 kΩ internal pull-up.	–
102	GMAC_LED3_PHYAD2	VDD_3V3	Input/Output	Programmable LED3 output/PHYAD2	–
101	GMAC_LED2_PHYAD1	VDD_3V3	Input/Output	Programmable LED2 output/PHYAD1	–
100	GMAC_LED1_PHYAD0	VDD_3V3	Input/Output	Programmable LED1 output/PHYAD0	–
99	GMAC_NRST	VDD_3V3	Input	Gigabit PHY reset line. 10 kΩ internal pull-up.	Low
166	SEL_VLDO1	5V_MAIN	Input	VLDO1 Default Output Voltage Selection pin. Three-state input.	–
165	MCP16502_HPM	5V_MAIN	Input	High-Power Mode Input pin. In combination with PWRHLD and LPM, this pin defines the MCP16502 power mode status.	High
154	nSTART_SOM	5V_MAIN	Input/Pull-up	Start event input. Drives nSTART_SOM to low to initiate a start-up sequence. nSTART_SOM is pulled up internally. A capacitor can be connected to automatically initiate a power-up sequence when the main supply rises.	Low

29

MIPI_CK_N

VDD_2V5

PHY

MIPI DPHY negative differential output clock lane

–

30

MIPI_CK_P

VDD_2V5

PHY

MIPI DPHY positive differential output clock lane

–

25

MIPI_D0_N

VDD_2V5

PHY

MIPI DPHY negative differential output data lane 0

–

26

MIPI_D0_P

VDD_2V5

PHY

MIPI DPHY positive differential output data lane 0

–

27

MIPI_D1_N

VDD_2V5

PHY

MIPI DPHY negative differential output data lane 1

–

28

MIPI_D1_P

VDD_2V5

PHY

MIPI DPHY positive differential output data lane 1

–

31

MIPI_D2_N

VDD_2V5

PHY

MIPI DPHY negative differential output data lane 2

–

32

MIPI_D2_P

VDD_2V5

PHY

MIPI DPHY positive differential output data lane 2

–

33

MIPI_D3_N

VDD_2V5

PHY

MIPI DPHY negative differential output data lane 3

–

34

MIPI_D3_P

VDD_2V5

PHY

MIPI DPHY positive differential output data lane 3

–

185

USBA_P

VDD_3V3

USBPHY

USB host port A high-speed data +

–

184

USBA_N

VDD_3V3

USBPHY

USB host port A high-speed data -

–

187

USBB_P

VDD_3V3

USBPHY

USB host port B high-speed data +

–

186

USBB_N

VDD_3V3

USBPHY

USB host port B high-speed data -

–

189

USBC_P

VDD_3V3

USBPHY

USB host port C high-speed data +

–

188

USBC_N

VDD_3V3

USBPHY

USB host port C high-speed data -

–

130

PIOBU0

VBAT

Backup I/O

Tamper input/output 0 / Wake-up 2 input

–

132

PIOBU1

VBAT

Backup I/O

Tamper input/output 1 / Wake-up 3 input

–

131

PIOBU2

VBAT

Backup I/O

Tamper input/output 2 / Wake-up 4 input

–

133

PIOBU3

VBAT

Backup I/O

Tamper input/output 3 / Wake-up 5 input

–

134

JTAGSEL

VBAT

Backup I/O

JTAG selection

–

129

WKUP

VBAT

Backup I/O

Wake-up input. 100 kΩ internal pull-up.

–

135

SHDN

VBAT

Backup I/O

Shutdown control

Low

173

NRST

VDD_3V3

Input/Output

External nReset input/output. 10 kΩ internal pull-up.

Low

174

NRST_OUT

VDD_3V3

Output I/O

Microprocessor reset output

Low

147

AUDIOCLK

VDD_3V3

Output

Audio clock output

–

162

RSV0

–

Reserved. Connect to GND.

–

163

RSV1

–

Reserved. Connect to GND.

–

97

NAND_WP

VDD_3V3

Input

NAND Flash write protect. 100 kΩ internal pull-up.

Low

49

NAND_CS_IN

VDD_3V3

Input

NAND Flash chip select input. 100 kΩ internal pull-up.

Low

77

QSPI0_CS_IN

VDD_3V3

Input

NOR Flash chip select input. 10 kΩ internal pull-up.

Low

109

TXRXA_P

VDD_1V1_ETH

Input/Output

Physical receive or transmit signal (+ differential)

–

110

TXRXA_M

VDD_1V1_ETH

Input/Output

Physical receive or transmit signal (– differential)

–

112

TXRXB_P

VDD_1V1_ETH

Input/Output

Physical receive or transmit signal (+ differential)

–

113

TXRXB_M

VDD_1V1_ETH

Input/Output

Physical receive or transmit signal (– differential)

–

115

TXRXC_P

VDD_1V1_ETH

Input/Output

Physical receive or transmit signal (+ differential)

–

116

TXRXC_M

VDD_1V1_ETH

Input/Output

Physical receive or transmit signal (– differential)

–

118

TXRXD_P

VDD_1V1_ETH

Input/Output

Physical receive or transmit signal (+ differential)

–

119

TXRXD_M

VDD_1V1_ETH

Input/Output

Physical receive or transmit signal (– differential)

–

104

GMAC_LED5_ALLPHYAD

VDD_3V3

Input/Output

Programmable LED5 output/PHY Address Strap pin

–

103

GMAC_LED4_MAGJACK

VDD_3V3

Input/Output

Programmable LED4 output/MagJack register settings. 10 kΩ internal pull-up.

–

102

GMAC_LED3_PHYAD2

VDD_3V3

Input/Output

Programmable LED3 output/PHYAD2

–

101

GMAC_LED2_PHYAD1

VDD_3V3

Input/Output

Programmable LED2 output/PHYAD1

–

100

GMAC_LED1_PHYAD0

VDD_3V3

Input/Output

Programmable LED1 output/PHYAD0

–

99

GMAC_NRST

VDD_3V3

Input

Gigabit PHY reset line. 10 kΩ internal pull-up.

Low

166

SEL_VLDO1

5V_MAIN

Input

VLDO1 Default Output Voltage Selection pin. Three-state input.

–

165

MCP16502_HPM

5V_MAIN

Input

High-Power Mode Input pin. In combination with PWRHLD and LPM, this pin defines the MCP16502 power mode status.

High

154

nSTART_SOM

5V_MAIN

Input/Pull-up

Start event input. Drives nSTART_SOM to low to initiate a start-up sequence. nSTART_SOM is pulled up internally. A capacitor can be connected to automatically initiate a power-up sequence when the main supply rises.

Low