39.8.5 WRITE_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK Operation using DMA Controller

  1. Wait until the current command execution has successfully terminated.
    1. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR.
  2. Program the block length in the card. This value defines the value block_length.
  3. Program the block length in the HSMCI Configuration Register with block_length value.
  4. Configure the fields of the HSMCI_MR as follows:
    1. Program FBYTE to one when the transfer is not multiple of 4, zero otherwise.
  5. Issue a WRITE_SINGLE_BLOCK command writing HSMCI_ARGR then HSMCI_CMDR.
  6. Program the DMA Controller.
    1. Read the Channel Status Register to choose an available (disabled) channel.
    2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the DMAC_CISx register.
    3. Program the channel registers.
    4. The DMAC_CSAx register for Channel x must be set to the location of the source data.
    5. The DMAC_CDAx register for Channel x must be set with the starting address of the HSMCI_FIFO address.
    6. Configure the fields of DMAC_CCx of Channel x as follows:
      • DWIDTH is set to WORD when the transfer is multiple of 4, otherwise it is set to BYTE
      • CSIZE must be set according to the value of HSMCI_DMA.CHKSIZE
    7. Configure the fields of DMAC_CUBCx for Channel x as follows:
      • UBLEN is programmed with block_length/4 when the transfer length is multiple of 4, block_length otherwise
    8. Enable Channel x, writing one to DMAC_GE.EN[x]. The DMAC is ready and waiting for request.
  7. Wait for XFRDONE in the HSMCI_SR.